參數(shù)資料
型號： LFX200B-05FN256C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 26/119頁
文件大?。?/td> 0K
描述： IC FPGA 200K GATES 256-BGA
標準包裝： 90
系列： ispXPGA®
邏輯元件/單元數(shù)： 2704
RAM 位總計： 113664
輸入/輸出數(shù)： 160
門數(shù)： 210000
電源電壓： 2.3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應商設備封裝： 256-FPBGA（17x17）
Lattice Semiconductor
ispXPGA Family Data Sheet
10
Figure 10. ispXPGA PIC
Programmable Input/Output
The PIO is the building block of a PIC. The PIO has a total of 11 inputs and five outputs. Nine of the 11 inputs are
generated from routing. The inputs from routing are the PIO Input (IN), Feed-Thru (FT), Clock (CLK), Input Clock
Enable (ICE), Input Set/Reset (ISR), Output Clock Enable (OCEN), Output Set/Reset (OSR), PIO Output Enable
(OEN), and PIO Input Enable (IEN). The remaining inputs are the sysIO input buffer signal and the Global Set/
Reset signal. Three of the five outputs (OUT0, OUT1, and OE) feed routing. The last two outputs feed the sysIO
buffer directly as the output and output enable of the sysIO output buffer.
PIOs associated with sysHSI blocks contain two additional inputs and outputs to support the sysHSI block. The two
inputs come from the sysHSI block associated with the PIO, and the two outputs feed the sysHSI block. One of the
inputs routes directly through the PIO to routing, while the other is multiplexed with the Feed-Thru, register bypass,
and Q output of the register to form the OUT1 output of the PIO. The outputs to the sysHSI block are the same sig-
nals as the outputs which feed the sysIO buffers (sysIO Output and sysIO Output Enable).
Each PIO has an input register, an output register, and an output enable register as shown in Figure 11. The input
register path of the PIO has a ‘delay’ option, which slows the data-flow. A two-input OR function of the Global Set/
Reset (GSR) and Set/Reset (ISR or OSR) signals creates the set/reset term for the respective registers. Each PIO
has two pairs of set/reset and clock enable signals. One is exclusive to the input register, whereas the other is com-
mon for both the output and output enable registers. The clock (CLK) is common to all registers in a PIO, and the
polarity of the clock is controllable. The input, output, and the output enable registers can be configured as a latch
or D-type flip-flop. Each PIO is capable of generating an output enable signal, which in turn becomes a PIC output.
PIC
PIO0
PIO1
OE1 OE0
sysIO
9
2
To routing
Only for PICs
associated with
sysHSI blocks
Only for PICs
associated with
sysHSI blocks
To routing
From routing
GSR
sysIO
From sysHSI block
To sysHSI block
2
9
From sysHSI block
To sysHSI block
2
SELECT
DEVICES
DISCONTINUED
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相關代理商/技術參數(shù)
參數(shù)描述
LFX200B-05FN516C 功能描述:FPGA - 現(xiàn)場可編程門陣列 210K Gt ispJTAG 2.5 /3.3V -5 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX200B-05FN516C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX200B-3F256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX200B-3F256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX200B-3F516C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
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