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參數(shù)資料
| 型號(hào)： | LG1600FXH |
| 廠商： | Lineage Power |
| 英文描述： | Clock and Data Regenerator(時(shí)鐘數(shù)據(jù)再生器) |
| 中文描述： | 時(shí)鐘和數(shù)據(jù)再生（時(shí)鐘數(shù)據(jù)再生器） |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 492K |
| 代理商： | LG1600FXH |
Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
5
Lucent Technologies Inc.
Theory of Operation
(continued)
A more useful expression of the PLL characteristics is
the following
*
:
The jitter transfer is now directly expressed in the phys-
ical loop gain pole product,
ω
b
, and the loop filter time
constant,
τ
. Damping ratio,
,
and natural frequency,
ω
n
,
simply relate to these two parameters as follows:
and
* Wolaver, D.H., Phase-Locked Loop Circuit Design Prentice Hall,
1991.
H s
ω
b
1
-------------------------------------
s
τ
1
+
1
s
τ
s
ω
b
1
-----
+
+
=
ω
b
τ
0.5
=
ω
n
ω
n
τ
=
For moderate damping
> 2.5
(ω
b
τ
< 0.1), the –3 dB
bandwidth of the PLL can be approximated by the loop
gain pole product:
J
BW
≈
ω
b
= K
d
R
x
K
o
while the jitter peaking can be expressed in terms of
the product of PLL bandwidth and loop filter time con-
stant:
b
τ
As the last two expressions make clear, the PLL band-
width is controlled by the value of the external resistor
(see Figure 8), while the peaking depends both on the
resistor value (quadratically) and total loop filter capac-
itance.
H s
max
1
--1
+
≈
1
R
x
2
CK
d
K
o
----------1
+
=
12-3231(F)r.4—12-3232(F)r.4
Figure 8. Jitter Bandwidth vs. External Resistor Value
0
50
100
200
250
0.0
0.2
0.6
0.8
1.0
1.2
Rx (
)
0.4
150
A. LG1600FXH0622 (Cx = 0.15
μ
F)
10
°
C
70
°
C
25
°
C
J
B
0
50
100
200
250
0.0
0.6
1.8
2.4
3.0
3.6
Rx (
)
1.2
150
B. LG1600FXH2488 (Cx = 0)
10
°
C
J
B
25
°
C
70
°
C
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