參數(shù)資料
型號(hào): LH28F016SUT-10
廠(chǎng)商: Sharp Corporation
英文描述: 16M (1M x 16 , 2M x 8) Flash Memory
中文描述: 1,600(100萬(wàn)× 16,200萬(wàn)× 8)閃存
文件頁(yè)數(shù): 30/37頁(yè)
文件大?。?/td> 326K
代理商: LH28F016SUT-10
LH28F016SU
16M (1M × 16, 2M × 8) Flash Memory
30
Figure 15. AC Waveforms for Command Write Operations
ADDRESSES (A)
(NOTE 1)
V
IH
V
IL
A
IN
A = RA
V
IH
V
IL
A
IN
A = RA
D
IN
D
IN
D
IN
D
IN
D
OUT
CE
(E)
(NOTE 4)
V
IH
V
IL
OE (G)
V
IH
V
IL
WE (W)
V
IH
V
IL
DATA (D/Q)V
IH
V
IL
RY/BY (R)V
OH
V
OL
RP (P)
V
IH
V
IL
t
AVAV
t
AVAV
t
WHGL
t
WHWL
t
WLWH
t
DVWH
t
PHWL
t
RHPL
t
QVVL
ADDRESSES (A)
(NOTE 2)
t
AVWH
t
WHAX
t
AVWH
t
WHAX
t
ELWL
t
WHEH
t
WHQV 1, 2
t
GHWL
t
WHDX
t
WHRL
(NOTE 5)
t
VPWH
28F016SUT-13
(NOTE 3)
HIGH-Z
WRITE
DATA-WRITE
OR ERASE
SETUP COMMAND
DEEP
POWER-DOWN
WRITE VALID
ADDRESS AND DATA
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
WRITE READ
EXTENDED
REGISTER
COMMAND
READ
EXTENDED
STATUS
REGISTER DATA
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CE
X
is defined as the latter of CE
0
or CE
1
going LOW or the first of CE
0
or CE
1
going HIGH.
5. RP low transition is only to show t
RHPL
; not valid for above Read and Write cycles.
READ
COMPATIBLE
STATUS
REGISTER DATA
V
PP
(V)
V
PPH
V
PPL
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