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參數(shù)資料
| 型號： | LH52256C |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 256K (32K x 8) Static RAM |
| 中文描述： | 的CMOS 256K（32K的× 8）靜態(tài)RAM |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 97K |
| 代理商： | LH52256C |
DATA VALID
t
DH
t
DW
WE
D
IN
t
CW
ADDRESS
t
WC
52256C-5
t
WR
t
AW
CE
t
AS
t
WZ
t
WP
(NOTE 2
)
(NOTE 4)
(NOTE 3)
D
OUT
(NOTE 6)
(NOTE 1)
t
WR
t
OW
(NOTE 7)
(NOTE 5)
(NOTE 4)
1. A write occurs during the overlap of a LOW CE, and a LOW WE.
A write begins at the latest transition among CE going LOW, and
WE going LOW. A write ends at the earliest transition among CE
going HIGH, and WE going HIGH. t
WP
is measured from the beginning
of write to the end of write.
2. t
CW
is measured from the later of CE going LOW to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change.
5. During this period, I/O pins are in the output state, therefore the input
signals of opposite phase to the outputs must not be applied.
6. If CE goes LOW simultaneously with WE going LOW or after WE going
LOW, the outputs remain in high impedance state.
7. If CE goes HIGH simulaneously with WE going HIGH or before WE
going HIGH, the outputs remain in high impedance state.
NOTES:
Figure 6. Write Cycle (OE Low Fixed)
t
CDR
V
CC
4.5 V
2.2 V
V
CCDR
0 V
CE
CE
≥
V
CCDR
- 0.2 V
DATA RETENTION MODE
t
R
52256C-6
CE
CONTROL
Data Retention Timing Chart
CE Controlled
LH52256C/CH
CMOS 256K (32K
×
8) Static RAM
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH52256CH | CMOS 256K (32K x 8) Static RAM |
| LH52258A | CMOS 32K x 8 Static RAM |
| LH525C2T | 256K SRAM |
| LH525C9N | 256K SRAM |
| LH525CL2 | 256K SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH52256C-10LL | 制造商:Sharp Microelectronics 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 100ns 28-Pin PDIP |
| LH52256C-70LL | 功能描述:IC SRAM 256KBIT 70NS 28DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| LH52256CD-10LL | 制造商:Sharp Microelectronics 功能描述:32KX8 SRAM |
| LH52256CD-70LL | 制造商:Sharp Microelectronics 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin PDIP |
| LH52256CH | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:CMOS 256K (32K x 8) Static RAM |
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