參數資料
型號: LH7A400
廠商: Sharp Corporation
英文描述: 32-Bit System-on-Chip
中文描述: 32位系統級芯片
文件頁數: 28/53頁
文件大小: 446K
代理商: LH7A400
LH7A400
32-Bit System-on-Chip
28
12/8/03
Preliminary Data Sheet
External Bus Interface
The external bus interface allows the ARM922T,
LCD controller and DMA engine access to an external
memory system. The LCD controller has access to an
internal frame buffer in embedded SRAM and an exten-
sion buffer in Synchronous Memory for large displays.
The processor and DMA engine share the main system
bus, providing access to all external memory devices
and the embedded SRAM frame buffer.
An arbitration unit ensures that control over the
External Bus Interface (EBI) is only granted when an
existing access has been completed. See Figure 5.
Embedded SRAM
The amount of Embedded SRAM contained in the
LH7A400 is 80KB. This Embedded memory is designed
to be used for storing code, data, or LCD frame data
and to be contiguous with external SDRAM. The 80KB
is large enough to store a QVGA panel (320 × 240) at 8
bits per pixel, equivalent to 70KB of information.
Containing the frame buffer on chip reduces the
overall power consumed in any application that uses
the LH7A400. Normally, the system has to perform
external accesses to acquire this data. The LCD con-
troller is designed to automatically use an overflow
frame buffer in SDRAM if a larger screen size is
required. This overflow buffer can be located on any
4KB page boundary in SDRAM, allowing software to
set the MMU (in the LCD controller) page tables such
that the two memory areas appear contiguous. Byte,
Half-Word and Word accesses are permissible.
Asynchronous Memory Controller
The Asynchronous memory controller is incorpo-
rated as part of the memory controller to provide an
interface between the AMBA AHB system bus and
external (off-chip) memory devices.
The Asynchronous Memory Controller provides sup-
port for up to eight independently configurable memory
banks simultaneously. Each memory bank is capable
of supporting:
SRAM
ROM
Flash EPROM
Burst ROM memory.
Each memory bank may use devices using either 8-,
16-, or 32-bit external memory data paths. The memory
controller can be configured to support either little-
endian or big-endian operation.
The memory banks can be configured to support:
Non-burst read and write accesses only to high-
speed CMOS static RAM.
Non-burst write accesses, nonburst read accesses
and asynchronous page mode read accesses to
fast-boot block flash memory.
Figure 4. Memory Mapping for Each Boot Mode
ASYNCHRONOUS MEMORY (nCS0)
SYNCHRONOUS MEMORY (nSCS2)
F000.0000
E000.0000
SYNCHRONOUS MEMORY (nSCS1)
D000.0000
C000.0000
SYNCHRONOUS MEMORY (nSCS0)
RESERVED
EMBEDDED SRAM
B001.4000
B000.0000
RESERVED
8000.3800
8000.2000
AHB INTERNAL REGISTERS
APB INTERNAL REGISTERS
8000.0000
7000.0000
ASYNCHRONOUS MEMORY (CS7)
ASYNCHRONOUS MEMORY (CS6)
6000.0000
5000.0000
PCMCIA/CompactFlash (nPCSLOTE2)
PCMCIA/CompactFlash (nPCSLOTE1)
4000.0000
ASYNCHRONOUS MEMORY (nCS3)
ASYNCHRONOUS MEMORY (nCS2)
2000.0000
3000.0000
1000.0000
ASYNCHRONOUS MEMORY (nCS1)
SYNCHRONOUS ROM (nSCS3)
0000.0000
SYNCHRONOUS MEMORY BOOT
SYNCHRONOUS MEMORY (nSCS3)
SYNCHRONOUS MEMORY (nSCS2)
SYNCHRONOUS MEMORY (nSCS1)
SYNCHRONOUS MEMORY (nSCS0)
RESERVED
EMBEDDED SRAM
RESERVED
AHB INTERNAL REGISTERS
APB INTERNAL REGISTERS
ASYNCHRONOUS MEMORY (CS7)
ASYNCHRONOUS MEMORY (CS6)
PCMCIA/CompactFlash (nPCSLOTE2)
PCMCIA/CompactFlash (nPCSLOTE1)
ASYNCHRONOUS MEMORY (nCS3)
ASYNCHRONOUS MEMORY (nCS2)
ASYNCHRONOUS MEMORY (nCS1)
ASYNCHRONOUS ROM (nCS0)
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
80KB
256MB
256MB
256MB
ASYNCHRONOUS MEMORY BOOT
LH7A400-6
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