參數(shù)資料
型號(hào)： LH7A400
廠商： Sharp Corporation
英文描述： 32-Bit System-on-Chip
中文描述： 32位系統(tǒng)級(jí)芯片
文件頁(yè)數(shù)： 6/53頁(yè)
文件大小： 446K
代理商： LH7A400
LH7A400
32-Bit System-on-Chip
6
12/8/03
Preliminary Data Sheet
M13
K16
K15
K14
J8
J16
J14
J9
H16
H14
G16
G14
G13
F16
L15
K12
K13
K16
J13
J11
J16
H15
H10
H12
G15
G10
G11
F16
A2/SA0
A3/SA1
A4/SA2
A5/SA3
A6/SA4
A7/SA5
A8/SA6
A9/SA7
A10/SA8
A11/SA9
A12/SA10
A13/SA11
A14/SA12
A15/SA13
Asynchronous Address Bus
Synchronous Address Bus
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
F14
E16
A16/SB0
Asynchronous Address Bus
Synchronous Device Bank Address 0
Asynchronous Address Bus
Synchronous Device Bank Address 1
LOW
LOW
12 mA
E16
F13
A17/SB1
LOW
LOW
12 mA
E13
F11
D15
C16
B16
A15
A13
E14
D15
C16
C15
C14
B15
E11
A18
A19
A20
A21
A22
A23
A24
Asynchronous Address Bus
LOW
LOW
12 mA
G8
D8
A25/SCIO
Asynchronous Memory Address Bus
Smart Card Interface I/O (Data)
Asynchronous Memory Address Bus
Smart Card Interface Clock
Asynchronous Memory Address Bus
Smart Card Interface Reset
Asynchronous Memory Output Enable
Asynchronous Memory Write Byte Enable 0
Asynchronous Memory Write Byte Enable 3
Asynchronous Memory Chip Select 6
Synchronous Memory Clock Enable 1 OR 2
Asynchronous Memory Chip Select 7
Synchronous Memory Clock Enable 0
Synchronous Memory Clock Enable 3
LOW: A25
LOW
12 mA
F8
B7
A26/SCCLK
LOW: A26
LOW
12 mA
A8
A7
A27/SCRST
LOW: A27
LOW
12 mA
D8
C8
D10
C8
F8
D9
nOE
nWE0
nWE3
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
12 mA
12 mA
8 mA
B10
E9
CS6/SCKE1_2
LOW: CS6
LOW
12 mA
C10
A10
CS7/SCKE0
LOW: CS7
LOW
12 mA
G9
A11
SCKE3
LOW
LOW
12 mA
20 mA
(sink)
12 mA
(source)
12 mA
12 mA
12 mA
12 mA
12 mA
A10
B10
SCLK
Synchronous Memory Clock
LOW
LOW
C14
D13
E11
A12
C12
C13
A15
D11
E10
A13
nSCS0
nSCS1
nSCS2
nSCS3
nSWE
Synchronous Memory Chip Select 0
Synchronous Memory Chip Select 1
Synchronous Memory Chip Select 2
Synchronous Memory Chip Select 3
Synchronous Memory Write Enable
Synchronous Memory Column Address
Strobe Signal
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
C11
B11
nCAS
HIGH
HIGH
12 mA
Table 1. Functional Pin List (Cont’d)
PBGA
PIN
CABGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
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