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參數(shù)資料
| 型號： | LH7A400N0C000 |
| 廠商： | Sharp Corporation |
| 英文描述： | 32-Bit System-on-Chip |
| 中文描述： | 32位系統(tǒng)級芯片 |
| 文件頁數(shù)： | 26/53頁 |
| 文件大小： | 446K |
| 代理商： | LH7A400N0C000 |
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LH7A400
32-Bit System-on-Chip
26
12/8/03
Preliminary Data Sheet
Power Modes
The LH7A400 has three operational states: Run,
Halt, and Standby. In Run mode, all clocks are hard-
ware-enabled and the processor is clocked. Halt mode
stops the processor clock while waiting for an event
such as a key press, but the device continues to func-
tion. Finally, Standby equates to the computer being
switched ‘off’, i.e. no display (LCD disabled) and the
main oscillator is shut down. The 32.768 kHz oscillator
operates in all three modes.
Reset Modes
There are three external signals that can generate
resets to the LH7A400; these are nPOR (power on
reset), nPWRFL (power failure) and nURESET (user
reset). If any of these are active, a system reset is gen-
erated internally. A nPOR reset performs a full system
reset. The nPWRFL and nURESET resets will perform
a full system reset except for the SDRAM refresh con-
trol, SDRAM Global Configuration, SDRAM Device
Configuration and the RTC peripheral registers. The
SDRAM controller will issue a self-refresh command to
external SDRAM before the system enters this reset
(the nPWRFL and nURESET resets only, not so for the
nPOR reset). This allows the system to maintain its
Real Time Clock and SDRAM contents. On coming out
of reset, the chip enters Standby mode. Once in Run
mode the PWRSR register can be interrogated to deter-
mine the nature of the reset, and the trigger source,
after which software can then take appropriate actions.
Data Paths
The data paths in the LH7A400 are:
The AMBA AHB bus
The AMBA APB bus
The External Bus Interface
The LCD AHB bus
The DMA busses.
AMBA AHB BUS
The Advanced Microprocessor Bus Architecture
Advanced High-performance Bus (AMBA AHB) bus is a
high speed 32-bit-wide data bus. The AMBA AHB is for
high-performance, high clock frequency system modules.
Peripherals that have high bandwidth requirements
are connected to the LH7A400 core processor using
the AHB bus. These include the external and internal
memory interfaces, the LCD registers, palette RAM
and the bridge to the Advanced Peripheral Bus (APB)
interface. The APB Bridge transparently converts the
AHB access into the slower speed APB accesses. All
of the control registers for the APB peripherals are pro-
grammed using the AHB - APB bridge interface. The
main AHB data and address lines are configured using
a multiplexed bus. This removes the need for tri-state
buffers and bus holders, and simplifies bus arbitration.
Figure 3. Clock and State Controller Block Diagram
14.7456 MHz
MAIN OSC.
HCLK
32.768 kHz
RTC OSC.
/2, /4, /8
PCLKs
FCLK
HCLK
(TO PROCESSOR CORE)
LH7A400-4
STATE CONTROLLER
DIVIDE REGISTER
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH7A400N0E000 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:32-Bit System-on-Chip |
| LH7A400N0E000B3A | 功能描述:IC ARM922T MCU 200MHZ 256CABGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:BlueStreak ; LH7A 標(biāo)準(zhǔn)包裝:96 系列:PIC® 16F 核心處理器:PIC 芯體尺寸:8-位 速度:20MHz 連通性:I²C，SPI 外圍設(shè)備:欠壓檢測/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):11 程序存儲器容量:3.5KB（2K x 14） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:128 x 8 電壓 - 電源 (Vcc/Vdd):2.3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 包裝:管件 |
| LH7A400N0E000B3A,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A400N0E000B5,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A400N0F000B3A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:32-Bit System-on-Chip |
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