參數(shù)資料
型號(hào): LH7A400N0C000
廠商: Sharp Corporation
英文描述: 32-Bit System-on-Chip
中文描述: 32位系統(tǒng)級(jí)芯片
文件頁數(shù): 41/53頁
文件大?。?/td> 446K
代理商: LH7A400N0C000
32-Bit System-on-Chip
LH7A400
Preliminary Data Sheet
12/8/03
41
Synchronous Memory Controller Waveforms
Figure 9 shows the waveform and timing for a Syn-
chronous Burst Read (page already open). Figure 10
shows the waveform and timing for Synchronous mem-
ory to Activate a Bank and Write.
Figure 9. Synchronous Burst Read
Figure 10. Synchronous Bank Activate and Write
t
SCLK
LH7A400-23
SA[13:0],
SB[1:0]
D[31:0]
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC.
4. DQM[3:0] is static LOW.
5. SCKE is static HIGH.
SCLK
SDRAMcmd
nDQM
t
OVXXX
t
OVA
t
OHXXX
READ
BANK,
COLUMN
tOVA
tISD tIHD
DATA n
DATA n + 1
DATA n + 2
DATA n + 3
LH7A400-24
D[31:0]
SCLK
SCKE
SDRAMcmd
tSCLK
tOVC
tOVXXX
tOVA
tOHXXX
tOVA
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC.
4. DQM[3:0] is static LOW.
ACTIVE
WRITE
DATA
BANK,
ROW
BANK,
COLUMN
tOVD
tOHD
SA[13:0],
SB[1:0]
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