Control Register Definitions (Continued)
ROM Signature Control Register (I
2C address 840Dh).
REGISTER NAME: ROMSIGCTRL
Bit 7
Bit 0
RSV
CRS
Bit 0:
Calculate ROM Signature. Setting this bit causes the entire ROM to be read, sequentially, and a 16 bit CRC calculated
over its contents. The residual value from this calculation is placed in the ROM Signature Data register. This bit
automatically clears itself when the calculation has been completed.
Bits 7–1:
RESERVED.
ROM Signature Data Register (I
2C address 840Eh–840Fh).
REGISTER NAME: ROMSIGDATAB1 (840Fh) ROMSIGDATAB0 (840Eh)
Bit 15
Bit 8
Bit 7
Bit 0
CRC15 CRC14 CRC13 CRC12 CRC11 CRC10
CRC9
CRC8
CRC7
CRC6
CRC5
CRC4
CRC3
CRC2
CRC1
CRC0
Bits 15–0: ROM Signature Data. This register indicates the residual value from the CRC calculation. Devices containing ROMs
with different programming will give different signatures. Devices with the same ROM programming will give the same
signature.
Display Window 1 Horizontal Pixel Start Location Register (I
2C address 8410h).
REGISTER NAME: HSTRT1 (8410h)
Bit 7
Bit 0
1H7
1H6
1H5
1H4
1H3
1H2
1H1
1H0
Bits 7–0: Display Window 1 Horizontal Pixel Start Location. These seven bits determine the starting horizontal pixel location,
which is determined by multiplying the value of these bits by 4 and adding 30 pixels. Due to pipeline delays, the first
usable location for the OSD window is approx 42 pixels to the right of the horizontal flyback pulse. For this reason, the
display start location must be programmed with a number larger than 2, otherwise improper operation may occur.
This byte must be set so the entire OSD window is within the active video.
Display Window 1 Vertical Pixel Start Location Register (I
2C address 8411h).
REGISTER NAME: VSTRT1 (8411h)
Bit 7
Bit 0
1V7
1V6
1V5
1V4
1V3
1V2
1V1
1V0
Bits 7–0: Display Window 1 Vertical Pixel Start Location. These eight bits determine the starting vertical pixel location in
constant height character lines, which is determined by multiplying the value of these bits by 2. (Note, each character
line is treated as a single auto-height character pixel line, so multiple scan lines may actually be displayed in order to
maintain accurate position relative to the character cell size — See
Constant Character Height Mechanism section.)
This byte must be set so the entire OSD window is within the active video.
Display Window 1 Column Width Control Register (I
2C address 8414h–8417h).
REGISTER NAME: COLWIDTH1B3 (8417h) COLWIDTH1B2 (8416h) COLWIDTH1B1 (8415h) COLWIDTH1B0 (8414h)
Bit 31
Bit 24
Bit 23
Bit 16
COL31
COL30
COL29
COL28
COL27
COL26
COL25
COL24
COL23
COL22
COL21
COL20
COL19
COL18
COL17
COL16
Bit 15
Bit 8
Bit 7
Bit 0
COL15
COL14
COL13
COL12
COL11
COL10
COL9
COL8
COL7
COL6
COL5
COL4
COL3
COL2
COL1
COL0
Bits 31–0: Display Window 1 Column Width 2x Enable Bits. These thirty-two bits correspond to columns 31–0 of Display
Window 1, respectively. A value of zero indicates the column will have normal width (12 pixels). A value of one
indicates the column will be twice as wide as normal (24 pixels). For the double wide case, each Character Font pixel
location will be displayed twice, in two consecutive horizontal pixel locations.
The user should note that if more than 32 display characters are programmed to reside on a row, then all display
characters after the first thirty-two will have normal width (12 pixels).
LM1253A
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