參數(shù)資料
型號(hào): LM2324
廠(chǎng)商: National Semiconductor Corporation
英文描述: PLLatinum⑩ 2.0 GHz Frequency Synthesizer for RF Personal Communications
中文描述: PLLatinum⑩射頻個(gè)人通訊2.0 GHz的頻率合成器
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 157K
代理商: LM2324
Connection Diagrams
Pin Descriptions
Pin No.
Pin
Name
V
P
CP
o
I/O
Description
TSSOP16
2
3
CSP16
1
2
O
Power supply for charge pump. Must be
V
CC
Internal charge pump output. For connection to a loop filter for driving the
voltage control input of an external oscillator.
Ground.
RF prescaler complimentary input. In single-ended mode, a bypass
capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane. The LMX2324 can be driven
differentially when the bypass capacitor is omitted.
RF prescaler input. Small signal input from the voltage controlled oscillator.
No Connect
No Connect
Oscillator input. A CMOS inverting gate input. The input has a V
CC
/2 input
threshold and can be driven from an external CMOS or TTL logic gate.
No Connect
High impedance CMOS Clock input. Data is clocked in on the rising edge,
into the various counters and registers.
Binary serial data input. Data entered MSB first. LSB is control bit. High
impedance CMOS input.
Load Enable input. When Load Enable transitions HIGH, data is loaded
into either the N or R register (control bit dependent). See timing diagram.
No Connect
No Connect
CHIP Enable. A LOW on CE powers down the device asynchronously and
will TRI-STATE
the charge pump output.
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass
capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
4
5
3
4
GND
f
INB
I
6
7
8
9
5
6
7
8
f
IN
NC
NC
OSC
in
I
I
10
12
9
NC
Clock
10
I
13
11
Data
I
14
12
LE
I
15
11
16
13
14
15
NC
NC
CE
I
1
16
V
CC
I
TSSOP 16-Pin Package
DS101030-2
Order Number LMX2324TM, LM2324TMX
See NS Package Number MTC16
CSP 16-Pin Package
DS101030-3
Top View
Order Number LMX2324SLBX
See NS Package Number SLB16A
L
www.national.com
2
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