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參數(shù)資料
| 型號： | LM2457 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 823K |
| 代理商： | LM2457 |
Absolute Maximum Ratings
(Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
80V Voltage, V
CC1
120V Supply V
CC2
Bias Voltage, V
BB
Input Voltage, V
IN
V
BLANK
Input Voltage, V
BLANK
Storage Temperature Range, T
STG
Lead Temperature
(Soldering,
<
10 sec.)
ESD Tolerance, Human Body
Model
+90V
+130V
+15V
0V to 4V
0V to V
BB
V
65C to +150C
300C
2 kV
ESD Tolerance, Machine Model
200V
Limits of Operating Ranges
(Note 2)
V
CC1
V
BOOST
V
BB
V
IN
V
REF
V
BLANK
Input Voltage, V
BLANK
V
OUT
V
CLAMP
Case Temperature
+60V to +85V
V
CC1
to +125V
7.0V to +9V
0.8V to +3.5V
+1.6V to +1.9V
0V to 5.5V
+15V to +75V
+55V to +118V
20C to 100C
AC Driver Electrical Characteristics
(See Figure 4 for Test Circuit)
Unless otherwise noted: V
= +80V
, V
= +8V
, V
IN
= 2.50V
DC
, C
L
= 8pF, Output = 40V
PP
(25-65) at 1MHz, T
C
= 50C,
V
REF
= 1.735V
DC
, HEATSINK MUST BE GROUNDED.
Symbol
Parameter
Conditions
I
CC1MAX
V
CC
Supply Current
All 3 Channels, No Output Load
I
BBMAX
Maximum Bias Current
All 3 Channels
V
OUTTYP
Typical DC Output Voltage
V
IN
= 2.100 V
DC
A
VTYP
Typical DC Voltage Gain
No AC Input Signal
T
RTYP
Typical Rise Time
10% to 90%, (Note 5)
+OS
Overshoot on Rising Edge
t
FTYP
Typical Fall Time
90% to 10%, (Note 5)
OS
Overshoot on Falling Edge
LE
TYP
Typical Linearity Error
V
IN
2.0 V
DC
to 3.0 V
DC
, (Note 4)
Min
Typ
32
15
65
52
7.5
5
7.5
1
6
Max
Units
mA
mA
V
DC
61
69
ns
%
ns
%
%
Note 1:
Limits of “Absolute Maximum Ratings” indicate limits below which damage to the device will not occur.
Note 2:
Limits of “Operating Ratings” indicate required boundaries of conditions for which the device is functional, but is not guaranteed to meet specific performance
limits.
Note 3:
All voltages are measured with respect to GND, unless otherwise specified.
Note 4:
Linearity error is the variation in DC gain from V
IN
= 2.0V to 3.0V.
Note 5:
Input from signal generator: t
r
, t
f
<
1ns.
Driver Test Circuit
Figure 4 shows the test circuit for the LM2457. This circuit allows testing of the LM2457 in a 50
environment as well as with a
FET probe. The 4950
resistor at the output forms a 200:1 voltage divider when connected to a 50
load. C
COMP
is used to
flatten the frequency response of the 200:1 divider. Performance will be affected slightly by the 5K load.
DS101379-4
FIGURE 4. Test Circuit (One Channel)
L
www.national.com
3
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