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參數(shù)資料
| 型號： | LM2457 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 823K |
| 代理商： | LM2457 |
Application Hints
(Continued)
Effect of Load Capacitance
Figure 10 shows the effect of increased load capacitance on
the speed of the device. This demonstrates the importance
of knowing the load capacitance in the application. It is
important to note that the rise time of the series R in the test
circuit in Figure 4 along with the load capacitance will in-
crease its contribution to the speed degradation as the load
capacitance is increased. The previous section discussed
how to optimize the transient response in the application with
the use of a series inductor.
Effect of Offset
Figure 9 shows the variation in rise and fall times when the
output offset of the device is varied from 40 VDC to 50 VDC.
The rise time shows a maximum variation relative to the
center data point (45 VDC) of less than 6%. The fall time
shows a variation of about 6% relative to the center data
point.
It is recommended that the video black level be set about
10V below the V
CC
power supply in the application (Black
level at
～
70 with V
CC
= 80 V
DC
). This will give the best
overall performance while also minimizing the DC power
dissipation.
DC CLAMP AMPLIFIERS
The portion of the multiplexed input signal that is below the
reference voltage controls the DC clamp amplifiers. The DC
transfer function of the amplifier is shown in Figure 12
Figure 15 shows the application circuit for the clamp ampli-
fier. Clamp diode D1 is placed as close as possible to the
video node to minimize trace lengths and parasitic capaci-
tance. Pull-up resistor R1 is required to bias the PNP output
stage of the clamp circuit. Capacitor C2 provides a low
impedance at high frequencies and helps minimize clamp
level variation that could be caused by changes in the cath-
ode current.
INTEGRATED BOOST SUPPLY AND G1 BLANK
CIRCUIT
Upon initial power up the G1 V
blank
/Cap Low input will sink
current until the boost capacitor is charged up to approxi-
mately 43V (V
CC1
–V
G1-L
). After this initial charge up period,
the voltage across the boost capacitor will be replenished
during the vertical blank interval.
The charge cycle will be initiated by the V
input signal
(negative going, logic level pulse). Figure 16 shows the
boost application circuit. During the charge cycle the voltage
at pin 4 will be set to
～
36V and capacitor C28 will be charged
to
～
43V through diode D11. When the charge cycle is com-
pleted, the voltage at pin 4 will be set to
～
79V and the plus
side of the boost cap will be at
～
122V
DC
. The pin 2 side of
capacitor C29 will then be charged to
～
121.3V (0.7V below
122) through D12. Diode D12 is required to avoid turning on
the ESD protection diodes between the video clamp outputs
and the 120V pin during the charge cycle. C29 is required to
maintain the 120V at pin 2 during the charge cycle.
The 43Vp-p pulse at pin 4 can be ac-coupled to G1 of the
CRT to blank the CRT during vertical retrace. The recom-
mended application circuit for doing this is shown in Figure
18
THERMAL CONSIDERATIONS
Figure 6 shows the performance of the LM2457 video am-
plifiers in the test circuit shown in Figure 4 as a function of
case temperature. The figure shows that the rise time of the
LM2457 decreases by approximately 4% as the case tem-
perature increases from 50C to 100C. This corresponds to
a speed degradation of
<
1% for every 10C rise in case
temperature. There is a negligible change in fall time versus
temperature in the test circuit.
Figure 8shows the total power dissipation of the LM2457 vs.
frequency when all three video channels of the device are
driving an 8 pF or 12pF load with a 40V
signal. The graph
assumes a 72% active time (device operating at the speci-
fied frequency) which is typical in a monitor application. The
other 28% of the time the device is assumed to be sitting at
the black level (65V in this case). This graph gives the
designer the information needed to determine the heat sink
requirement for his application. It is important to note that the
capacitive load dramatically effects the AC component of the
total power dissipation.
The LM2457 case temperature must be maintained below
100C. If the maximum expected ambient temperature is
50C and the maximum power dissipation is 8.5W, then a
maximum heat sink thermal resistance can be calculated:
This example assumes a capacitive load of 8 pF, no resistive
load and a maximum operating frequency of 50 MHz or
greater.
THE NSC REFERENCE DESIGN
Figures 17, 18, 19 show the schematic and layout for the
NSC Neck Board Reference Design. It contains a complete
video channel from monitor input to CRT cathode. Perfor-
mance is ideal for 1024 X 768 resolution displays with pixel
DS101379-21
FIGURE 15. Clamp Application Circuit.
DS101379-20
FIGURE 16. Boost Circuit Schematic
L
www.national.com
8
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