參數(shù)資料
型號(hào): LM2501SL
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer
中文描述: LINE TRANSCEIVER, QCC24
封裝: 3.50 X 4.50 MM, 0.60 MM HEIGHT, CSP-24
文件頁(yè)數(shù): 5/14頁(yè)
文件大?。?/td> 302K
代理商: LM2501SL
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
PARALLEL BUS TIMING
t
SET
Set Time - Data to Clock
t
HOLD
Hold Time - Clock to Data
t
RISE
Rise Time
t
FALL
Fall Time
PC
LOW
PCLK Low
PC
HIGH
PCLK High
t
DVBC
Data Valid before Clock
t
DVAC
Data Valid after Clock
SERIAL BUS TIMING
t
DVBC
t
DVAC
POWER UP TIMING (see
Figures 5, 6
)
t
1
WC Start Up Delay
t
2
WC Low Initialization Low
State
t
3
WC Pulse Width High
t
4
WC Low State
t
5
WC
IN
to WC
OUT
Latency
(SER)
t
6
TBD
t
7
SER PLL Lock Time
t
8
MC Low Initialization Low
State
t
9
MC Pulse Width High
t
10
MC Low State
t
11
SER Latency
t
12
DES Latency
POWER OFF TIMING
t
PAZ
Disable Time to Power Off
t
PZA
Enable Time from Power
Off
Parameter
Conditions
Min
Typ
Max
Units
Inputs
Figure 2
TBD
TBD
ns
ns
ns
ns
%
%
ns
ns
Outputs,
C
L
= 15 pF
50
50
Figure 2
TBD
TBD
Figure 1
Figure 5
Planned Rev G ES test Chip will
double WC cyc counts on T
1
to T
4
(SER) parameters to support higher
WC rates.
100
WC
CYC
11
12
13
WC
CYC
11
11
12
12
13
13
WC
CYC
WC
CYC
6
7
8
WC
CYC
9
WC
CYC
MC
CYC
Figure 6
4,096
11
12
13
MC
CYC
11
11
12
12
TBD
TBD
13
13
MC
CYC
MC
CYC
MC
CYC
MC
CYC
μs
μs
L
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