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參數(shù)資料
| 型號(hào)： | LM2633MTD |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs |
| 中文描述： | SWITCHING CONTROLLER, 275 kHz SWITCHING FREQ-MAX, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁(yè)數(shù)： | 33/40頁(yè) |
| 文件大?。?/td> | 1350K |
| 代理商： | LM2633MTD |
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Control Loop Design
(Continued)
TABLE 5. R1 and R2 Values vs. VID
VID4:0
V
DAC
(V)
R
1
R
2
r =
R2/(R1+R2)
0.41
0.42
0.41
0.46
0.43
0.47
0.47
0.55
0.49
0.52
0.51
0.58
0.54
0.59
0.59
0.72
0.65
0.67
0.66
0.72
0.69
0.73
0.73
0.82
0.76
0.79
0.78
0.86
0.81
0.87
0.87
1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
17.1k
18.4k
17.4k
21.4k
19.3k
22.0k
22.1k
30.0k
24.5k
27.3k
26.0k
34.6k
29.3k
36.0k
36.4k
64.3k
23.2k
25.7k
24.5k
32.1k
27.5k
33.3k
33.6k
56.2k
39.6k
47.4k
43.4k
75.0k
53.7k
81.8k
83.7k
∞
NO CPU
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1. 075
1.050
1.025
1.000
0.975
0.95
0.925
0.900
The signal path from output voltage to control voltage is the
feedback path. It typically contains a voltage divider, an error
amplifier and a compensation network. Those are shown In
Figure 7 as R
1
, R
2
, the gm amplifier, and Z
c
. For Channel 1
of the LM2633, since an R-2R ladder network is used, R
1
and R
values change with the VID setting. For information
regarding their values and ratios, refer to Table 5 For Chan-
nel 2, R
1
and R
2
are simply the external voltage divider
resistors.
To achieve the gain shape in Figure 10 Z
in Figure 7should
take the form of two RC branches in parallel, as shown in
Figure 11 In the scheme, C1 and R3 form the first zero f
z1
,
C2 and R3 form the second pole f
p2
, and C2 and R4 form the
second zero f
z2
.
The gain of the compensation network can be calculated as
the following. If the ESR zero frequency f
z
is higher than the
low frequency pole f
p
, then there should be a 20dB/decade
section from f
(310 Hz) to f
(8.8 kHz) in the plant gain plot,
such as shown in Figure 9 Find the frequency where this
section (or the extension of this section) crosses 0dB by
using the following equation:
f
c_o
= M
f
p
If the desired loop transfer function cross-over frequency is
f
, then the gain of the compensation network at f
p
should
be:
(41)
(42)
To determine the component values in Figure 11 the follow-
ing equations can be used:
(43)
where B is the desired gain at f
z1
, and g
m
is the transcon-
ductance of the error amplifier.
(44)
20000864
FIGURE 10. 2-Pole 2-Zero (lag-lag) Network Asymptotic
Gain Plot
20000865
FIGURE 11. Compensation Network
L
www.national.com
33
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