![](http://datasheet.mmic.net.cn/390000/LM2647LQX_datasheet_16815461/LM2647LQX_17.png)
Application Information
(Continued)
selected if the output voltage ripple needs to be decreased but it is not
desirable to achieve this by adding more (expensive) output specialty
caps.
The peak current under normal operation is
Conclusions:
In this example the peak inductor current
under normal operation is 3.7A. Usually it is necessary only
to set the current limit about 20% higher than the peak value.
This ‘overload margin’ helps greatly in handling sudden load
changes.A20% margin would have required the current limit
to be set at 3.7*120%=4.44A (for a steady state peak of
3.7A). Therefore RLIM would need to be
A standard resistor value of 1.78k can be chosen in the
example. However, a larger overload margin than the cho-
sen 20% (say 40%) is recommended for obtaining good
dynamic response if the load could suddenly change from
extremely low values (zero to a few mA) right up to maximum
load
current.
In
this
I
=3.7*140%=5.2A, requiring RLIM to be 18.2m*5.2/
46μ=2.05k (available as a standard value).
Note that excessively high current limits (large RLIM values)
will generate severe stresses in the FETs during abnormal
load condition (like a shorted output for example). These
peak currents will be even higher if the inductor saturates
sharply. The designer must evaluate the actual application
for the expected and actual step loads so as to select RLIM
more optimally. Then it should be decided how much over-
load margin is really required, and RLIM selected accord-
ingly. The equations to do this are provided in this section,
but the judgement must remain with the designer, as it
depends on the specific application on hand.
Repeating the calculation for a 10μH inductor for a 3.3V/3A
rated output, and any low side equivalent FET (with the
same Rds as Si4420DY) we get the following requirement:
For 20% overload margin, select current limit resistor to be
1.69k
For 40% overload margin, select current limit resistor to be
1.96k
Note that if the lower FET Rds is different from the one used
in the example above, the current limit resistor RLIM must be
recalculated according the new Rds.
For the evaluation board the selected FET was a dual pack
Si4828DY. Its worst case hot Rds is 24.5m
. Setting current
limit as 5.5A, the estimated current limit resistor is 5.5 x 24.5
/ 46 = 2.93k
. A standard value of 2.94k
was chosen for
the Bill of Materials.
case,
it
would
require
INDUCTOR and OUTPUT CAPACITOR
The designer is again referred to AN-1197 for the equations
required here. In general, ‘r’ is the key parameter and once
that is chosen, the inductance can be calculated. The design
table in the referenced Application Note uses V
as the drop
across the diode in an asynchronous configuration. Also,
V
SW
is the drop across the Switch (upper FET). In the case
of the LM2647 a reasonable approximation is to set V
D
=
V
SW
= 0 in the design table available in AN-1197. Then the
table can be used easily for selection of the inductor and
output capacitor. A step by step example is also provided for
a general buck regulator in the Application Note AN-1207 at
http://power.national.com.
Only in the case of the input capacitor, the situation may be
different as is explained next.
INPUT CAPACITOR
In a typical single-channel buck regulator, the input capacitor
provides most of the pulsed current waveform demanded by
the Switch. However the DC (average) value of the current
through a capacitor in steady state must be zero. Otherwise,
the capacitor would start accumulating charge every cycle,
and that would clearly not represent a ‘steady state’ by
definition.
Now for the LM2647, there are two ways of calculating and
meeting the input capacitance requirement. One way is to
use separate input capacitors for each channel (as in the
Evaluation board). The other possibility is to combine them
into a single component. There are advantages and disad-
vantages to each approach.
By keeping separate input capacitors the possibility of inter-
action between the two channels is reduced, and the layout
is a little more forgiving. But two components would require
more board space and could also add to the cost. Though in
general, there could also be a situation where the cost of a
single component is equal to (or even exceeds) the com-
bined cost of two separate capacitors. The reason cost can
be surely reduced when using one input capacitor in the
LM2647 is because the two channels run 180 out of phase
(interleaved switching). It can be shown that this dramatically
reduces the ripple current requirement at the input. See
Figure 12
for typical waveforms to understand how this
happens. Remember that ‘frequency’ does not (directly) en-
ter into any computations of RMS values, so the use of
interleaved switching is clearly going to produce a lower
RMS value as can be guessed by eyeballing the waveforms
shown in
Figure 12
.
20056327
FIGURE 12. Switch and Input Capacitor Currents
L
www.national.com
17