PWM Mode
(Continued)
compensation ramp from the oscillator is subtracted from the
error signal for stability of the current feedback loop. The
minimum on-time of PFET in PWM mode is 50 ns (typ).
Bypass Mode
The LM3200 contains an internal PFET switch for bypassing
the PWM DC-DC converter during Bypass mode. In Bypass
mode, this PFET is turned on to power the PA directly from
the battery for maximum RF output power. When the part
operates in the Bypass mode, the output voltage will be the
input voltage less the voltage drop across the resistance of
the bypass PFET. Bypass mode is more efficient than oper-
ating in PWM mode at 100% duty cycle because the resis-
tance of the bypass PFET is less than the series resistance
of the PWM PFET and inductor. This translates into higher
voltage available on the output in Bypass mode, for a given
battery voltage. The part can be placed in bypass mode by
sending BYP pin high. This is called Forced Bypass Mode
and it remains in bypass mode until BYP pin goes low.
Alternatively the part can go into Bypass mode automatically.
This is calledAuto-bypass mode orAutomatic Bypass mode.
The bypass switch turns on when the difference between the
input voltage and programmed output voltage is less than
250 mV (typ.) for more than the bypass delay time of 15 μs
(typ.). The bypass switch turns off when the input voltage is
higher than the programmed output voltage by 450 mV (typ.)
for longer than the bypass delay time. The bypass delay time
is provided to prevent false triggering into Automatic Bypass
mode by either spikes or dips in V
IN
. This method is very
system resource friendly in that the Bypass PFET is turned
on automatically when the input voltage gets close to the
output voltage, typical scenario of a discharging battery. It is
also turned off automatically when the input voltage rises,
typical scenario of a charger connected. Another scenario
could be changes made to V
voltage causing Bypass
PFET to turn on and off automatically. It is recommended to
connect BYPOUT pin directly to the output capacitor with a
separate trace and not to the FB pin.
Operating Mode Selection Control
The BYP digital input pin is used to select between PWM/
Auto-bypass and Bypass operating mode. Setting BYP pin
high (
>
1.2V) places the device in Forced Bypass mode.
Setting BYP pin low (
<
0.4V) or leaving it floating places the
device in PWM/Auto-bypass mode.
Bypass and PWM operation overlap during the transition
between the two modes. This transition time is approxi-
mately 31 μs when changing from PWM to Bypass mode,
and 15 μs when changing from Bypass to PWM mode. This
helps prevent under or overshoots during the transition pe-
riod between PWM and Bypass modes.
Shutdown Mode
Setting the EN digital pin low (
<
0.4V) places the LM3200 in
a 0.1 μA (typ.) Shutdown mode. During shutdown, the PFET
switch, NFET synchronous rectifier, reference voltage
source, control and bias circuitry of the LM3200 are turned
off. Setting EN high (
>
1.2V) enables normal operation.
EN should be set low to turn off the LM3200 during power-up
and under voltage conditions when the power supply is less
than the 2.7V minimum operating voltage. The LM3200 is
designed for compact portable applications, such as mobile
phones. In such applications, the system controller deter-
mines power supply sequencing and requirements for small
package size outweigh the benefit of including UVLO (Under
Voltage Lock-Out) circuitry.
Dynamically Adjustable Output
Voltage
The LM3200 features dynamically adjustable output voltage
to eliminate the need for external feedback resistors. The
output can be set from 0.8V to 3.6V by changing the voltage
on the analog V
CON
pin. This feature is useful in PA applica-
tions where peak power is needed only when the handset is
far away from the base station or when data is being trans-
mitted. In other instances, the transmitting power can be
reduced. Hence the supply voltage to the PA can be re-
duced, promoting longer battery life. See
Setting the Output
Voltage
in the
Application Information
section for further
details.
Over Voltage Protection
The LM3200 has an over voltage comparator that prevents
the output voltage from rising too high. If the output voltage
rises to 330 mV over its target, the OVP comparator inhibits
PWM operation to skip pulses until the output voltage returns
to the target. Typically the OVP comparator may be activated
during V
steps particularly steps from a high to a low
voltage. During the over voltage protection mode, both the
PWM PFET and the NFET synchronous rectifier are off.
When the part comes out of the over voltage protection
mode, the NFET synchronous rectifier remains off for ap-
proximately 3.5 μs to avoid inductor current going negative.
Internal Synchronous Rectification
While in PWM mode, the LM3200 uses an internal NFET as
a synchronous rectifier to reduce rectifier forward voltage
drop and associated power loss. Synchronous rectification
provides a significant improvement in efficiency whenever
the output voltage is relatively low compared to the voltage
drop across an ordinary rectifier diode.
With medium and heavy loads, the internal NFET synchro-
nous rectifier is turned on during the inductor current down
slope in the second part of each cycle. The synchronous
rectifier is turned off prior to the next cycle. There is no zero
cross detect, which means that the NFET can conduct cur-
rent in both directions and inductor current is always con-
tinuous. The advantage of this method is that the part re-
mains in PWM mode at light loads or no load conditions. The
NFET has a current limit. The NFET is designed to conduct
through its intrinsic body diode during transient intervals
before it turns on, eliminating the need for an external diode.
Current Limiting
A current limit feature allows the LM3200 to protect itself and
external components during overload conditions. In PWM
mode, a 940 mA (max.) cycle-by-cycle current limit is nor-
mally used. If an excessive load pulls the output voltage
down to below approximately 0.375V, indicating a possible
short to ground, then the device switches to a timed current
limit mode. In timed current limit mode, the internal PFET
switch is turned off after the current comparator trips, and the
beginning of the next cycle is inhibited for 3.5 μs to force the
instantaneous inductor current to ramp down to a safe value.
After the 3.5 μs interval, the internal PFET is turned on
again. This cycle is repeated until the load is reduced and
the output voltage exceeds approximately 0.375V. There-
L
www.national.com
12