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參數(shù)資料
| 型號： | LM322N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬波形發(fā)生器 |
| 英文描述： | Precision Timers |
| 中文描述： | RECTANGULAR, TIMER, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-14 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 281K |
| 代理商： | LM322N |
Pin Function Description
(Continued)
trollers. Typical temperature drift of the reference is less
than 0.01%/
§
C.
The
trigger
terminal is used to start a timing cycle (see
functional diagram). Initially, Q1 is saturated, C
t
is dis-
charged and the latching buffer output (V1) is latched high.
A trigger pulse unlatches the buffer, V1 goes low and turns
Q1 off. The timing capacitor C
t
connected from R/C to GND
will begin to charge. When the voltage at the R/C terminal
reaches the 2.0V threshold of the comparator, the compara-
tor toggles, latching the buffer output (V1) in the high state.
This turns on Q1, discharges the capacitor C
t
and the cycle
is ready to begin again.
If the
trigger
is held high as the timing period ends, the
comparator will toggle and V1 will go high exactly as before.
However, V1 will not be latched and the capacitor will not
discharge until the trigger again goes low. When the trigger
goes low, V1 remains high but is now latched.
Trigger
threshold is typically 1.6V at 25
§
C and has a tem-
perature dependence of
b
5.0 mV/
§
C. Current drawn from
the
trigger
source is typically 20
m
A at threshold, rising to
600
m
A at 30V, then leveling off due to FET action of the
series resistor, R5. For negative input trigger voltages, the
only current drawn is leakage in the nA region. The
trigger
can be driven from supplies as high as
g
40V, even when
device supply voltage is only 5V.
The
R/C
pin is tied to the non-inverting side of the compara-
tor and to the collector of Q1. Timing ends when the voltage
on this pin reaches 2.0V (1 RC time constant referenced to
the 3.15V regulator). Q1 turns on only if the trigger voltage
has dropped below threshold. In comparator or regulator
applications of the timer, the trigger is held permanently
high and the
R/C
pin acts just like the input to an ordinary
comparator. The maximum voltages which can be applied to
this pin are
a
5.5V and
b
0.7V. Current from the
R/C
pin is
typically 300 pA when the voltage is negative with respect to
the
V
ADJ
terminal. For higher voltages, the current drops to
leakage levels. In the boosted mode, input current is typical-
ly 30 nA. Gain of the comparator is very high, 200,000 or
more, depending on the state of the logic reverse pin and
the connection of the output transistor.
The
ground
pin of the LM122 need not necessarily be tied
to system ground. It can be connected to any positive or
negative voltage as long as the supply is negative with re-
spect to the
V
a
terminal. Level shifting may be necessary
for the input
trigger
if the
trigger
voltage is referred to sys-
tem ground. This can be done by capacitive coupling or by
actual resistive or active level shifting. One point must be
kept in mind; the emitter output must not be held above the
ground
terminal with a low source impedance. This could
occur, for instance, if the emitter were grounded when the
ground
pin of the LM122 was tied to a negative supply.
The terminal labled
V
ADJ
is tied to one side of the compara-
tor and to a voltage divider between
V
REF
and
ground
. The
divider voltage is set at 63.2% of V
REF
with respect to
groundDexactly one RC time constant. The impedance of
the divider is increased to about 30k with a series resistor to
present a minimum load on external signals tied to
V
ADJ
.
This resistor is a pinched type with a typical variation in
nominal value of
b
50%,
a
100% and a TC of 0.7%/
§
C. For
this reason, external signals (typically a pot between
V
REF
and
ground
) connected to
V
ADJ
should have a source re-
sistance as low as possible. For small changes in
V
ADJ
, up
to several k
X
is all right, but for large variations, 250
X
or
less should be maintained. This can be accomplished with a
1k pot, since the maximum impedance from the wiper is
250
X
. If a voltage is forced on
V
ADJ
from a hard source,
voltage should be limited to
b
0.5, and
a
5.0V, or current
limited to
g
1.0 mA. This includes capacitively coupled sig-
nals because even small values of capacitors contain
enough energy to degrade the input stage if the capacitor is
driven with a large, fast slewing signal. The
V
ADJ
pin may be
used to abort the timing cycle. Grounding this pin during the
timing period causes the timer to react just as if the capaci-
tor voltage had reached its normal RC trigger point; the
capacitor discharges and the output charges state. An ex-
ception to this occurs if the trigger pin is held high, when the
V
ADJ
pin is grounded. In this case, the output changes
state, but the capacitor does not discharge.
If the trigger drops while
V
ADJ
is being held low, discharge
will occur immediately and the cycle will be over. If the trig-
ger is still high when
V
ADJ
is released, the output may or
may not change state, depending on the voltage across the
timing capacitor. For voltages below 2.0V across the timing
capacitor, the output will change state immediately, then
once more as the voltage rises past 2.0V. For voltages
above 2.0V, no change will occur in the output. This pin is
not available on the LM2905/LM3905.
In noisy environments or in comparator-type applications, a
bypass capacitor on the
V
ADJ
terminal may be needed to
eliminate spurious outputs because it is high impedance
point. The size of the cap will depend on the frequency and
energy content of the noise. A 0.1
m
F will generally suffice
for spike suppression, but several
m
F may be used if the
timer is subjected to high level 60 Hz EMI.
The
emitter
and the
collector
outputs of the timer can be
treated just as if they were an ordinary transistor with 40V
minimum collector-emitter breakdown voltage. Normally, the
emitter
is tied to the
ground
pin and the signal is taken
from the
collector
, or the
collector
is tied to
V
a
and the
signal is taken from the
emitter
. Variations on these basic
connections are possible. The
collector
can be tied to any
positive voltage up to 40V when the signal is taken from the
emitter
. However, the
emitter
will not be pulled higher than
the supply voltage on the
V
a
pin. Connecting the
collector
to a voltage less than the
V
a
voltage is allowed. The
emit-
ter
should not be connected to a low impedance load other
than that to which the ground pin is tied. The transistor has
built-in current limiting with a typical knee current of 120 mA.
Temporary short circuits are allowed; even with
collector-
emitter
voltages up to 40V. The power x time product, how-
ever, must not exceed 15 watt-seconds for power levels
above the maximum rating of the package. A short to 30V,
6
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