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參數(shù)資料
| 型號： | LM32 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Dual Thermal Diode Temperature Sensor with SensorPath Bus |
| 中文描述： | 雙熱二極管溫度傳感器SensorPath總線 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 340K |
| 代理商： | LM32 |
3.0 Application Hints
(Continued)
q = 1.6x10
19
Coulombs (the electron charge),
T = Absolute Temperature in Kelvin
k = 1.38x10
23
joules/K (Boltzmann’s constant),
η
is the non-ideality factor of the process the diode is
manufactured on,
I
S
= Saturation Current and is process dependent,
I
f
= Forward Current through the base emitter junction
V
BE
= Base Emitter Voltage drop
In the active region, the -1 term is negligible and may be
eliminated, yielding the following equation
In the above equation,
η
and I
S
are dependant upon the
process that was used in the fabrication of the particular
diode. By forcing two currents with a very controlled ration
(N) and measuring the resulting voltage difference, it is
possible to eliminate the I
S
term. Solving for the forward
voltage difference yields the relationship:
The non-ideality factor,
η
, is the only other parameter not
accounted for and depends on the diode that is used for
measurement. Since
V
is proportional to both
η
and T,
the variations in
η
cannot be distinguished from variations in
temperature. Since the non-ideality factor is not controlled by
the temperature sensor, it will directly add to the inaccuracy
of the sensor. For the Pentium III Intel specifies a
±
1%
variation in
η
from part to part. As an example, assume a
temperature sensor has an accuracy specification of
±
3C at
room temperature of 25 C and the process used to manu-
facture the diode has a non-ideality variation of
±
1%. The
resulting accuracy of the temperature sensor at room tem-
perature will be:
T
ACC
=
±
3C + (
±
1% of 298 K) =
±
6 C
The additional inaccuracy in the temperature measurement
caused by
η
, can be eliminated if each temperature sensor is
calibrated with the remote diode that it will be paired with.
The following table shows the variations in non-ideality for a
variety of processors.
Processor Family
η
, non-ideality
Series
R
min
1
1
1.0057
typ
max
Pentium II
Pentium III CPUID 67h
Pentium III CPUID
68h/PGA370Socket/Celeron
Pentium 4, 423 pin
Pentium 4, 478 pin
1.0065 1.0173
1.0065 1.0125
1.008
1.0125
0.9933 1.0045 1.0368
0.9933 1.0045 1.0368
Pentium 4 on 0.13
micron process,
2-3.06GHz
Pentium 4 on 90 nm
process
Pentium M Processor
(Centrino)
MMBT3904
AMD Athlon MP model
6
1.0011 1.0021 1.0030 3.64
1.011
3.33
1.001511.002201.00289 3.06
1.003
1.008
1.002
1.016
3.2 PCB LAYOUT for MINIMIZING NOISE
In a noisy environment, such as a processor mother board,
layout considerations are very critical. Noise induced on
traces running between the remote temperature diode sen-
sor and the LM32 can cause temperature conversion errors.
Keep in mind that the signal level the LM32 is trying to
measure is in microvolts. The following guidelines should be
followed:
1.
Place the 100 pF and 0.1 μF power supply bypass
capacitors as close as possible to the LM32’s power pin.
Place the recommended thermal diode 100 pF capacitor
as close as possible to the LM32’s D+ and D pins.
Make sure the traces to the thermal diode 100 pF ca-
pacitor are matched.
2.
The recommended 100 pF diode capacitor actually has
a range of 0 pF to 3.3 nF (see curve in Typical Perfor-
mance Characteristics for effect on accuracy). The av-
erage temperature accuracy will not degrade. Increasing
the capacitance will lower the corner frequency where
differential noise error affects the temperature reading
thus producing a reading that is more stable. Con-
versely, lowering the capacitance will increase the cor-
ner frequency where differential noise error affects the
temperature reading thus producing a reading that is
less stable.
3.
Ideally, the LM32 should be placed within 10cm of the
Processor diode pins with the traces being as straight,
short and identical as possible. Trace resistance of 0.7
can cause as much as 1C of error. This error can be
compensated for by adding or subtracting an offset to
the remote temperature reading(s).
20071117
FIGURE 8. Ideal Diode Trace Layout
L
www.national.com
22
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