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參數(shù)資料
| 型號： | LM3311 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Step-Up PWM DC/DC Converter with Integrated LDO, Op-Amp, and Gate Pulse Modulation Switch |
| 中文描述： | 升壓的PWM直流/直流集成穩(wěn)壓器，運算放大器和開關(guān)門脈沖調(diào)制器 |
| 文件頁數(shù)： | 19/29頁 |
| 文件大小： | 2052K |
| 代理商： | LM3311 |
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Operation
(Continued)
INPUT UNDER-VOLTAGE PROTECTION
The LM3311 includes input under-voltage protection (UVP).
The purpose of the UVP is to protect the device both during
start-up and during normal operation from trying to operate
with insufficient input voltage. During start-up using a ramp-
ing input voltage the UVP circuitry ensures that the device
does not begin switching until the input voltage reaches the
UVP On threshold. If the input voltage is present and the
shutdown pin is pulled high the UVP circuitry will prevent the
device from switching if the input voltage present is lower
than the UVP On threshold. During normal operation the
UVP circuitry will disable the device if the input voltage falls
below the UVP Off threshold for any reason. In this case the
device will not turn back on until the UVP On threshold
voltage is exceeded.
LINEAR REGULATOR (LDO)
The LM3311 includes a Low Dropout Linear Regulator. The
LDO is designed to operate with ceramic input and output
capacitors with values as low as 2.2μF. The efficiency of the
LDO is approximately the output voltage divided by the input
voltage. When using higher input voltages special care
should be taken to not dissipate too much power and cause
excessive heating of the die. The power dissipated in the
LDO section is approximately:
P
D(LDO)
= (V
IN
- V
OUT
)*I
OUT
The LDO has an output undervoltage lockout feature. This
feature is to ensure the LDO will shut itself down in the event
of an output overload or short condition. When the output is
overloaded the output voltage will fall causing the ADJ volt-
age to fall. When the ADJ voltage falls to V
ADJ(LOW)
the LDO
will shut off. In this event the SHDN pin or the input UVP
must be cycled to turn the LDO back on.
The LDO output undervoltage lockout is controlled by the SS
voltage. The LDO startup time must be less than the follow-
ing:
T
S
= C
SS
*0.5V/I
SS
When SS is less than 0.5V the output undervoltage lockout
is disabled and allows the LDO to start up. When SS is
greater than 0.5V the undervoltage lockout is active. If the
LDO feedback voltage is not greater than V
when
SS reaches 0.5V the LDO may enter an undervoltage lock-
out condition. In most cases C
= 10nF or greater is suffi-
cient. If a supply other than that used to power V
is used to
power LV
care must be taken to apply the input voltage to
LV
IN
prior to applying voltage to V
IN
.
OPERATIONAL AMPLIFIER
Compensation:
The architecture used for the amplifier in the LM3311 re-
quires external compensation on the output. Depending on
the equivalent resistive and capacitive distributed load of the
TFT-LCD panel, external components at the amplifier out-
puts may or may not be necessary. If the capacitance pre-
sented by the load is equal to or greater than an equivalent
distibutive load of 50
in series with 4.7nF no external
components are needed as the TFT-LCD panel will act as
compensation itself. Distributed resistive and capacitive
loads enhance stability and increase performance of the
amplifiers. If the capacitance and resistance presented by
the load is less than 50
in series with 4.7nF, external
components will be required as the load itself will not ensure
stability. No external compensation in this case will lead to
oscillation of the amplifier and an increase in power con-
sumption. A good choice for compensation in this case is to
add a 50
in series with a 4.7nF capacitor from the output of
the amplifier to ground. This allows for driving zero to infinite
capacitance loads with no oscillations, minimal overshoot,
and a higher slew rate than using a single large capacitor.
The high phase margin created by the external compensa-
tion will guarantee stability and good performance for all
conditions.
Layout and Filtering considerations:
When the power supply for the amplifier (AV
IN
) is connected
to the output of the switching regulator, the output ripple of
the regulator will produce ripple at the output of the amplifi-
ers. This can be minimized by directly bypassing theAV
IN
pin
to ground with a low ESR ceramic capacitor. For best noise
reduction a resistor on the order of 5
to 20
from the
supply being used to the AV
pin will create and RC filter
and give you a cleaner supply to the amplifier. The bypass
capacitor should be placed as close to the AV
pin as
possible and connected directly to the AGND plane.
For best noise immunity all bias and feedback resistors
should be in the low k
range due to the high input imped-
ance of the amplifier. It is good practice to use a small
capacitance at the high impedance input terminals as well to
reduce noise susceptibility. All resistors and capacitors
should be placed as close to the input pins as possible.
Special care should also be taken in routing of the PCB
traces. All traces should be as short and direct as possible.
The output pin trace must never be routed near any trace
going to the positive input. If this happens cross talk from the
output trace to the positive input trace will cause the circuit to
oscillate.
The op-amp is not a three terminal device it has 5 terminals:
positive voltage power pin, AGND, positive input, negative
input, and the output. The op-amp "routes" current from the
power pin andAGND to the output pin. So in effect an opamp
has not two inputs but four, all of which must be kept noise
free relative to the external circuits which are being driven by
the op-amp. The current from the power pins goes through
the output pin and into the load and feedback loop. The
current exiting the load and feedback loops then must have
a return path back to the op-amp power supply pins. Ideally
this return path must follow the same path as the output pin
trace to the load. Any deviation that makes the loop area
larger between the output current path and the return current
path adds to the probability of noise pick up.
GATE PULSE MODULATION
The Gate Pulse Modulation (GPM) block is designed to
provide a modulated voltage to the gate driver circuitry of a
TFT LCD display. Operation is best understood by referring
to the GPM block diagram in the
Block Diagrams
section, the
drawing in
Figure 2
and the transient waveforms in
Figure 3
and
Figure 4
.
There are two control signals in the GPM block, VDPM and
VFLK. VDPM is the enable pin for the GPM block. If VDPM
is high, the GPM block is active and will respond to the VFLK
drive signal from the timing controller. However, if VDPM is
low, the GPM block will be disabled and both PMOS
switches P2 and P3 will be turned off. The VGHM node will
be discharged through a 1k
resistor and the NMOS switch
N2.
When VDPM is high, typical waveforms for the GPM block
can be seen in
Figure 2
. The pin VGH is typically driven by
a 2x or 3x charge pump. In most cases, the 2x or 3x charge
L
www.national.com
19
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM3311_07 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Step-Up PWM DC/DC Converter with Integrated LDO, Op-Amp, and Gate Pulse Modulation Switch |
| LM3311SQ | 制造商:Texas Instruments 功能描述:CONVERTER DC/DC STEP UP LLP-24 |
| LM3311SQ/NOPB | 功能描述:IC REG BOOST ADJ 2A DL 24LLP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:降壓（降壓） 輸出類型:固定 輸出數(shù):1 輸出電壓:3.3V 輸入電壓:4.5 V ~ 24 V PWM 型:- 頻率 - 開關(guān):- 電流 - 輸出:125mA 同步整流器:無 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 包裝:Digi-Reel® 供應(yīng)商設(shè)備封裝:SOT-6 其它名稱:MAX1836EUT33#TG16DKR |
| LM3311SQ-HIOP | 功能描述:DC/DC 開關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| LM3311SQ-HIOP/NOPB | 功能描述:DC/DC 開關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
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