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參數(shù)資料
| 型號： | LM4550 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | Codec |
| 英文描述： | AC ’97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound |
| 中文描述： | 交流\u0026#39;97活2.1多聲道音頻編解碼器的立體聲耳機(jī)放大器，采樣率轉(zhuǎn)換和國家3D聲音 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 507K |
| 代理商： | LM4550 |
Pin Descriptions
(Continued)
DIGITAL I/O AND CLOCKING
Name
Pin
I / O
Functional Description
XTL_IN
2
I
24.576 MHz crystal input. Use a fundamental-mode type crystal. When operating from a
crystal, a 1M
resistor must be connected across pins 2 and 3.
24.576 MHz crystal output. When operating from a crystal, a 1M
resistor must be connected
across pins 2 and 3.
This data stream contains both control data and DAC audio data. This input is sampled by
the LM4550 on the falling edge of BIT_CLK.
OUTPUT when in Primary Codec Mode: This pin outputs a 12.288 MHz clock which is
derived (internally divided by two) from the 24.576MHz crystal input (XTL_IN).
INPUT when in Secondary Codec Mode (Multiple Codec configurations only): 12.288MHz
clock is to be supplied from an external source, such as from the BIT_CLK of a Primary
Codec.
This data stream contains both control data and ADC audio data. This output is clocked out
by the LM4550 on the rising edge of BIT_CLK.
48kHz sync pulse which signifies the beginning of both the SDATA_IN and SDATA_OUT
serial streams. SYNC must be synchronous to BIT_CLK.
This active low signal causes a hardware reset which returns the control registers to their
default conditions.
ID0 and ID1 set the codec address for multiple codec use where ID0 is the LSB. Connect
these pins to DVdd or GND as required. If these pins are not connected (NC), they default to
Primary codec setting (same as connecting both pins to DVdd). These pins are of inverted
polarity relative to their internal ID0, ID1 registers. If pin 45 is connected to GND, then ID0 will
be set to "1" internally. Connection to DVdd corresponds to a "0" internally.
ID0 and ID1 set the codec address for multiple codec use where ID1 is the MSB. Connect
these pins to DVdd or GND as required. If these pins are not connected (NC), they default to
Primary codec setting (same as connecting both pins to DVdd). These pins are of inverted
polarity relative to their internal ID0, ID1 registers. If pin46 is connected to GND, then ID1 will
be set to "1" internally. Connection to DVdd corresponds to a "0" internally.
The contents of "Powerdown Ctrl/Stat" register 26h bit 15 determines the logic level output on
this pin. This pin is to be connected to an external power amplifier’s shutdown pin. The output
voltage is set by the digital supply. If EAPD=0, then a logic low is output and the external
amplifer is enabled. If EAPD=1, the amplifer is shutdown. Power up default is EAPD=0.
By setting the two LSBs of register 74h to something other than the codec ID, the codec
stops sending its own SDATA_IN signal and instead passes the signal connected here out the
SDATA_IN pin. This pin can be left floating if no software will use register 74h and the chain
feature is not used. When the chain feature is used, another codec’s SDATA_IN pin should
be connected here, or else this pin should be grounded to prevent the possibility of floating
the SDATA_IN signal at the controller.
XTL_OUT
3
O
SDATA_OUT
5
I
BIT_CLK
6
I/O
SDATA_IN
8
O
SYNC
10
I
RESET#
11
I
ID0
45
I
ID1
46
I
EAPD
47
O
CHAIN_IN
48
I
POWER SUPPLIES AND REFERENCES
Name
AVDD
AVSS
DVDD
DVSS
Pin
25
26
1,9
4,7
I / O
I
I
I
I
Functional Description
Analog supply.
Analog ground.
Digital supply.
Digital ground.
Nominal 2.2V reference output. Not intended to sink or source current. Bypassing of this pin
should be done with short traces to maximize performance.
Nominal 2.2V reference output. Can source up to 5mA of current and can be used to bias a
microphone.
This pin is not used and should be left open (NC). However, a capacitor to ground on this pin
is permitted - it will not affect performance.
VREF
27
O
VREFOUT
28
O
AFILT1
29
O
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4550B | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:AC 97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound |
| LM4550BVH | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| LM4550BVH/NOPB | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| LM4550BVH/NOPB | 制造商:Texas Instruments 功能描述:Audio Codec IC |
| LM4550BVHX | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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