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參數(shù)資料
| 型號： | LM4550 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | Codec |
| 英文描述： | AC ’97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound |
| 中文描述： | 交流\u0026#39;97活2.1多聲道音頻編解碼器的立體聲耳機放大器，采樣率轉(zhuǎn)換和國家3D聲音 |
| 文件頁數(shù)： | 18/25頁 |
| 文件大?。?/td> | 507K |
| 代理商： | LM4550 |
Application Information
(Continued)
AC Link Input Frame: SDATA_IN (input to controller,
output from LM4550)
The audio input frame (input to the AC ’97 Digital Controller)
contains status and PCM data from the LM4550 control
registers and stereo ADC. The Tag slot, slot 0, contains 16
bits that tell theAC ’97 Digital Controller whether the LM4550
is ready and the validity of data from certain device subsec-
tions.
A new audio input frame is signaled with a low to high
transition of SYNC. SYNC is synchronous to the rising edge
of BIT_CLK. On the next rising edge of BIT_CLK, the
LM4550 drives SDATA_IN with the first bit of slot 0. The
Digital Controller samples SDATA_IN on the falling edge of
BIT_CLK.
The
LM4550
will
SDATA_IN stream on each successive rising edge of BIT-
_CLK. The LM4550 outputs data MSB first, in a MSB justi-
fied format. All reserved bits and slots are stuffed with "0" ’s
by the LM4550.
continue
outputting
the
SDATA_IN Slot 0: Codec Status Bits
The first bit of SDATA_IN Slot 0 (bit 15) indicates when the
Codec is ready. The digital controller must probe further to
see which other subsections are ready.
Bit
Description
Codec Ready
Bit
Slot 1 data
valid
Slot 2 data
valid
Slot 3 data
valid
Slot 4 data
valid
Comment
15
0=Not Ready, 1=Ready
14
Status Address is valid
13
Status Data is valid
12
Left Audio PCM Data is
valid
Right Audio PCM Data is
valid
11
SDATA_IN Slot 1: Status Address / Slot Request Bits
This slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read
request in the previous SDATA_OUT frame, slot 1. Bits 11
and 10 are slot request bits that support Sample Rate Con-
version (SRC) functionality. If bit 11 is set to 0, then the
controller should respond with a valid PCM left sample in slot
3 of the next frame. If bit 10 is set to 0, then the controller
should respond with a valid PCM right sample in slot 4 of the
next frame. If bits 11 or 10 are set to 1, the controller should
not send data in the next frame. Bits 9, 4, 3, and 2 are
unused. Bits 1 and 0 are reserved and should be set to 0.
Bits
19
Description
Reserved
Comment
Stuffed with "0"
Echo of Control Register
for which data is being
returned.
0 = Controller should send
valid slot 3 data in the next
frame, 1 = Controller
should not send slot 3 data
in the next frame
0 = Controller should send
valid slot 4 data in the next
frame, 1 = Controller
should not send slot 4 data
in the next frame
18:12
Control
Register Index
11
Slot 3 Request
bit (PCM left)
10
Slot 4 Request
bit (PCM right)
9
Slot 5 Request
bit
Unused - Stuff with "0"
8
Slot 6 Request
bit (PCM
Center)
0 = Controller should send
valid slot 6 data in the next
frame, 1 = Controller
should not send slot 6 data
in the next frame
0 = Controller should send
valid slot 7 data in the next
frame, 1 = Controller
should not send slot 7 data
in the next frame
0 = Controller should send
valid slot 8 data in the next
frame, 1 = Controller
should not send slot 8 data
in the next frame
0 = Controller should send
valid slot 9 data in the next
frame, 1 = Controller
should not send slot 9 data
in the next frame
7
Slot 7 Request
bit (PCM Left
Surround)
6
Slot 8 Request
bit (PCMRight
Surround)
5
Slot 9 Request
bit (PCM LFE)
4:2
Other Slot
Request bits
Reserved
Unused - stuff with "0"
1,0
Stuff with "0"
SDATA_IN Slot 2: Status Data
The slot returns the control register data. The data returned
was initiated by a read request in the previous SDATA_OUT
frame, slot 1.
Bits
Description
Control
Register Read
Data
Reserved
Comment
19:4
3:0
Stuffed with "0" ’s
10097207
FIGURE 7. Start of Audio Input Frame
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4550B | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:AC 97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound |
| LM4550BVH | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| LM4550BVH/NOPB | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| LM4550BVH/NOPB | 制造商:Texas Instruments 功能描述:Audio Codec IC |
| LM4550BVHX | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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