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參數(shù)資料
| 型號(hào)： | LM9800 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor |
| 中文描述： | 8位Greyscale/24-Bit彩色線陣CCD傳感器處理器 |
| 文件頁數(shù)： | 27/34頁 |
| 文件大?。?/td> | 619K |
| 代理商： | LM9800 |
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Applications Information
(Continued)
term. If OS is sampled at the end of period 3 and that voltage
is subtracted from the OS at the end of period 4, the
V
term is canceled and the noise on the signal is re-
duced. ([V
+V
]V
= V
SIGNAL
). This is
the principal of Correlated Double Sampling.
The LM9800 implements CDS with two switched-capacitor
S/H amplifiers. The S/Hs acquire a signal within a 50 ns win-
dow which can be placed anywhere in the pixel period with
25 ns precision. See Figures 7, 8 for more detailed timing in-
formation.
4.6 Offset DAC
The offset DAC is used to compensate for DC offsets due to
the correlated double sampling stage. The offset can be cor-
rected in 15 steps of 1 LSB size between 7 LSB and +7
LSB. Note that the DAC comes betore the PGA, so any off-
set errors at this stage are multiplied by the gain of the PGA.
The calibration procedure described in section 6.0 demon-
strates how to use the DAC to eliminate offset errors before
scanning begins.
Note
that
this
DAC
is
programmed
calibration/configuration and is not meant to compensate for
pixel-to-pixel CCD offset errors. (CDS cancels the pixel-rate
offset errors.)
during
LM9800
4.7 Programmable Gain Amplifier (PGA)
The PGAprovides 7 bits of pixeI-to-pixel gain correction over
a 0 dB to 6 dB (x1 to x2) range. After the input signal is
sampled and held by the CDS stage, it is amplified by the
gain indicated by the data (“PGA Code”) on the CD0–CD6
databus using the formula:
4.8 Offset Add Bit
In addition to the Offset DAC, there is a bit in the configura-
tion register which, when set, adds a positive 1 LSB offset at
the output of the PGA. This offset ensures that any offset be-
tween the output of the PGA and the ADC is positive, so that
no dark level information is lost due to negative offsets. The
calibration procedure described in section 6.0 demonstrates
how to set this bit.
4.9 ADC
The ADC converts the normalized analog output signal to an
8-bit digital code. The EOC output goes from high to low to
indicate that a new conversion is ready. ADC data can be
latched by external memory on the rising edge of EOC . The
RD input takes the ADC’s output buffer in and out of
TRI-STATE. RD may be tied to EOC in many applications,
putting the data on the bus only when EOC is low, and allow-
ing other data on the bus (such as CD0–CD6 correction
data) at other times. In this way the output data and correc-
tion coefficient data can share the same databus (see Figure
12).
4.10 I
SET
Input
This input is used to set internal bias currents inside the
LM9800. It should be tied to V
A
through a 75k
resistor.
5.0 COLOR
There are several ways to apply the LM9800 in a color sys-
tem:
5.1 Sequential RGB Output CCD
The solution shown in Figure 34 provides a 2.5Mpixels/sec
(830k RGB pixels/sec) pixel rate using a single LM9800 and
no additional external components. It requires a sequential
RGB output CCD, and provides inexpensive color at the ex-
pense of some resolution and registration.
5.2 Parallel Output CCD, One LM9800
Figure 35 gives an example of how to use a single LM9800
with a triple-output RGB CCD. In this case an entire line of
red is digitized, followed by an entire line of green, then blue.
This solution provides the same 2.5Mpixels/sec (for an effec-
tive 830k RGB pixels/sec after de-interleaving) pixel rate as
the previous solution but uses a higher performance color
CCD. The multiplexers select the color to be digitized and
the resistor tap voltage corresponding to the desired gain for
that color. The resistor ladder and its multiplexer can be re-
placed with a voltage output DAC (such as the DAC0854) for
precision digital control of the gain for each color.Almost any
multiplexer can be used since the multiplexer switches at the
line rate, not the pixel rate, and goes into a high impedance
input. The 74HC4052 is a good choice.
DS012498-41
FIGURE 34. Sequential RGB Output CCD
DS012498-42
FIGURE 35. Parallel Output CCD, One LM9800
27
www.national.com
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| LM9800CCV | 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor |
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| LM9811 | 10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM9800CCV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor |
| LM9800CCVF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Special Function Video Processor |
| LM9801 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Greyscale/24-Bit Color Linear CCD Sensor Processor |
| LM9801CCV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Greyscale/24-Bit Color Linear CCD Sensor Processor |
| LM9801CCVF | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Greyscale/24-Bit Color Linear CCD Sensor Processor |
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