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參數資料
| 型號： | LM9801CCVF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Greyscale/24-Bit Color Linear CCD Sensor Processor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數： | 5/34頁 |
| 文件大?。?/td> | 520K |
| 代理商： | LM9801CCVF |
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DC and Logic Electrical Characteristics
(Continued)
The following specifications apply for AGND
e
DGND
e
DGND
(I/O)
e
0V, V
A
e
V
D
e a
5.0V
DC
, V
D(I/O)
e a
5.0 or
a
3.0V
DC
, REF IN
e a
1.225V
DC
, f
MCLK
e
20 MHz, R
s
e
25
X
.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all
other limits T
A
e
T
J
e
25
§
C. (Notes 7 and 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
POWER SUPPLY CHARACTERISTICS
I
A
Analog Supply Current
Operating
Standby
25
50
32
mA (max)
m
A
I
D
Digital Supply Current
Operating
MCLK
e
0
6
8
mA (max)
m
A
65
I
D(I/O)
Digital I/O Supply Current
Operating, V
D(I/O)
e
5.0V
Operating, V
D(I/O)
e
3.0V
MCLK
e
0, V
D(I/O)
e
5.0V or 3.0V
3.1
1.6
1.7
6
4
mA (max)
mA (max)
mA
AC Electrical Characteristics, MCLK Independent
The following specifications apply for AGND
e
DGND
e
DGND
(I/O)
e
0V, V
A
e
V
D
e
V
D(I/O)
e a
5.0V
DC
, REF IN
e
a
1.225V
DC
, f
MCLK
e
20 MHz, t
MCLK
e
1/f
MCLK
, t
r
e
t
f
e
5 ns, R
s
e
25
X
, C
L
(databus loading)
e
50 pF/pin.
Boldface
limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C. (Notes 7 and 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
f
MCLK
Maximum MCLK Frequency
Minimum MCLK Frequency
20
1
MHz (min)
MHz (max)
MCLK Duty Cycle
30
70
40
60
% (min)
% (max)
t
A
SYNC Setup of MCLK
5
10
ns (min)
t
CDSETUP
Correction Data Valid to CLK Setup
14
20
ns (min)
t
CDHOLD
Correction Data Valid to CLK Hold
b
12
0
ns (min)
t
D1H
, t
D0H
RD High to DD0–DD7 TRI-STATE
5
15
ns (max)
t
DACC
Access Time Delay from RD Low to
DD0–DD7 Data Valid
15
30
ns (max)
f
SCLK
Maximum SCLK Frequency
20
MHz (min)
SCLK Duty Cycle
40
60
% (min)
% (max)
t
SDI
SDI Set-Up Time from SCLK
Rising Edge
3
10
ns (min)
t
HDI
SDI Hold Time from SCLK
Rising Edge
2
15
ns (min)
t
DDO
Delay from SCLK Falling Edge to
SDO Data Valid
25
50
ns (max)
t
HDO
SDO Hold Time from SCLK
Falling Edge
R
L
e
3k, C
L
e
50 pF
30
50
5
ns (max)
ns (min)
t
DELAY
DELAY from SCLK Falling Edge to
CS Rising or Falling Edge
5
10
ns (min)
t
SETUP
Set-Up Time of CS Rising or Falling
Edge to SCLK Rising Edge
0
10
ns (min)
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