參數(shù)資料
型號： LM9812
廠商： National Semiconductor Corporation
英文描述： LM9812 30-Bit Color Linear CCD Sensor Processor
中文描述： LM9812 30位彩色線陣CCD傳感器處理器
文件頁數(shù)： 6/37頁
文件大小： 479K
代理商： LM9812
6
http://www.national.com
t
WR HOLD
D0-D9 data valid after rising edge of
WR (hold time)
0
ns (min)
AC Electrical Characteristics, MCLK Dependent
The following specifications apply for AGND=DGND=DGND
I/O
=0V,
V
A
=
V
D
=
V
DI/O
=+5.0
V
DC
,
V
REF IN
= +2.0V
DC
, f
MCLK
=24MHz
,
t
MCLK
=1/f
MCLK
, t
r
=t
f
=5ns
, R
s
=25
, C
L
(databus loading) = 50pF/pin. Refer to Table 2: Configuration Register Parameters for limits
labeled C.R.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
t
R/S START
Rising edge of RUN/STOP to Rising
edge of SYNC
SYNC OUT mode
16
MCLKs (max)
t
START
Rising edge of SYNC to rising edge
of TR1
SYNC IN mode
SYNC IN mode
SYNC OUT mode
1+
t
GUARDBAND
13+
t
GUARDBAND
t
GUARDBAND
t
GUARDBAND
14+
GUARDBAND
t
GUARDBAND
MCLKs (min)
MCLKs (max)
MCLKs
t
SYNC END
Falling edge of SYNC to last rising
edge of EOC
SYNC IN mode
SYNC OUT mode
8
0
9
0
MCLKs (max)
MCLKs (max)
t
SYNC LOW
SYNC low time
SYNC IN mode
SYNC OUT mode
8
# of EOL
PIxels - 4
MCLKs (min)
Pixel periods
t
TR1 WIDTH
,
t
TR2 WIDTH
TR1, TR2 Transfer Pulse Width
C.R.
MCLKs
t
GUARD
TR1, TR2 Transfer Pulse Guardband
C.R.
MCLKs
t
RS WIDTH
Reset Pulse Width
C.R.
MCLKs
t
CLAMP ON
Start of Optical Black clamping
period
C.R.
MCLKs
t
CLAMP OFF
End of Optical Black clamping period
C.R.
MCLKs
t
1, 2 clock period
Standard Mode
Even/Odd Mode
12
24
MCLKs
MCLKs
t
RS
RS pulse position from 1 edge
C.R.
MCLKs
t
HOLD REF
Reference hold (sample) position
from RS edge
C.R.
MCLKs
t
HOLD SIG
Signal hold (sample) position from
RS edge
C.R.
MCLKs
t
OCLK LOW
OCLK low time (OCLK as Output)
2 bus mode
1bus mode
2*t
MCLK
1*t
MCLK
ns
t
OCLK HIGH
OCLK high time (OCLK as Output)
2 bus mode
1 bus mode
2*t
MCLK
3*t
MCLK
ns
t
GCLK LOW
GCLK low time (GCLK as Output)
2 bus mode
1 bus mode
2*t
MCLK
1*t
MCLK
ns
t
GCLK HIGH
GCLK high time (GCLK as Output)
2 bus mode
1 bus mode
2*t
MCLK
3*t
MCLK
ns
AC Electrical Characteristics, MCLK Independent
(Continued)
The following specifications apply for AGND=DGND=DGND
I/O
=0V,
V
A
=
V
D
=
V
DI/O
=+5.0
V
DC
,
V
REF IN
= +2.0V
DC
, f
MCLK
=24MHz
,
t
=1/f
, t
r
=t
f
=5ns
, R
s
=25, C
L
(databus loading) = 50pF/pin.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
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