參數(shù)資料
型號: LM9823CCWM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: LM9823 3 Channel 48-Bit Color Scanner Analog Front End
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封裝: 0.300 INCH, PLASTIC, SOIC-28
文件頁數(shù): 14/22頁
文件大?。?/td> 244K
代理商: LM9823CCWM
14
www.national.com
Table 2: Configuration Register Parameters
Note: Power-Up Default Register Settings are shown in
Bold Italics
Parameter
(Address)
Control Bits
Result
Sample Mode (0)
I/O Mode
(0)
B7
0
1
Normal Output Driver Operation
Reduced Slew Rate Output Driver Operation
DOE
(Data Output Edge)
(0)
B6
0
1
D7-D0 are clocked out (change) on the falling edge of MCLK - Recommended setting for
lowest noise and best overall performance.
D7-D0 are clocked out (change) on the rising edge of MCLK
CDS (Enable)
(0)
B5
0
1
CDS disabled (CIS)
CDS Enabled (CCD)
Signal Polarity
(0)
B4
0
1
Negative Polarity (CCD) Clamping to V
REF+
Positive Polarity (CIS) Clamping to V
REF-
SMPCL
(0)
B3
0
1
Clamp is on for 1 MCLK before reference sampled
Clamp is on between the reference and the signal sample points
CDSREF
(0)
B2
0
0
1
1
B1
0
1
0
1
Reference (for pixel N+1) sampled 1 MCLK cycle after signal (for pixel N) sampled
Reference (for pixel N+1) sampled 2 MCLK cycle after signal (for pixel N) sampled
Reference (for pixel N+1) sampled 3 MCLK cycle after signal (for pixel N) sampled
Reference (for pixel N+1) sampled 4 MCLK cycle after signal (for pixel N) sampled
PD
(Power Down)
(0)
B0
0
1
Operating
Low Power Standby
L
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