參數(shù)資料
型號(hào)： LM9823CCWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： LM9823 3 Channel 48-Bit Color Scanner Analog Front End
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： 0.300 INCH, PLASTIC, SOIC-28
文件頁(yè)數(shù)： 18/22頁(yè)
文件大小： 244K
代理商： LM9823CCWM
18
www.national.com
5.0 Offset DAC
The Offset DACs remove the DC offsets generated by the sensor
and the LM9823’s analog signal chain (see section 5.1, Internal
Offsets). The DAC value for each color (registers 1,2 and 3)
should be set during calibration to the lowest value that still
results in an ADC output code greater than zero for all the pixels
when scanning a black line. With a PGA gain of 1V/V, each LSB
of the offset DAC typically adds the equivalent of 20 ADC LSBs,
providing a total offset adjustment range of ±590 ADC LSBs. The
Offset DAC’s output voltage is given by:
In terms of 12 bit output codes, the offset is given by:
The offset is positive if bit B5 is cleared and negative if B5 is set.
Since the analog offset is added before the PGA gain, the value
of the PGA gain must be considered when selecting the offset
DAC values.
5.1 Internal Offsets
Figure 4 is a model of the LM9823’s internal offsets. Equation 4
shows how to calculate the expected output code given the input
voltage (VIN), the LM9823 internal offsets (V
, V
, V
),
the programmed offset DAC voltage (V
DAC
), the programmed
gains (G
B
, G
PGA
) and the analog channel gain constant C.
C is a constant that combines the gain error through the AFE, ref-
erence voltage variance, and analog voltage to digital code con-
version into one constant. Ideally, C = 2048 codes/V (4096
codes/2V) in 12 bit LSBs. Manufacturing tolerances widen the
range of C (see Electrical Specifications).
Figure 4. Internal Offset Model
Equation 4. Output code calculation with internal offsets
Equation 5 is a simplification of the output code calculation,
neglecting the LM9823’s internal offsets.
Equation 5. Simplified output code calculation
6.0 Clamping
To perform a DC restore across the AC coupling capacitors at the
beginning of every line, the LM9823 implements a clamping func-
tion. The clamping function is initiated by asserting the CLMP
input. If CLMP and VSMP are both high on a rising edge of
MCLK, all three OS inputs will be internally connected to V
or V
REF-
during the next pixel, depending on bit 4 of register 0. If
bit 4 is set to one (positive signal polarity), then the OS input will
be connected to V
REF-
. If bit 4 is set to zero (negative signal
polarity), then it will be connected to V
REF+
.
6.1 Clamp Capacitor Selection
The output signal of many sensors rides on a DC offset (greater
than 5V for many CCDs) which is incompatible with the LM9823’s
5V operation. To eliminate this offset without resorting to addi-
tional higher voltage components, the output of the sensor is AC
coupled to the LM9823 through a DC blocking capacitor, C
CLAMP
.
The sensor’s DOS output, if available, is not used. The value of
this capacitor is determined by the leakage current of the
LM9823’s OS input and the output impedance of the sensor. The
leakage through the OS input determines how quickly the capaci-
tor value will drift from the clamp value of V
or V
, which
then determines how many pixels can be processed before the
droop causes errors in the conversion (±0.1V is the recom-
mended limit for CDS operation). The output impedance of the
sensor determines how quickly the capacitor can be charged to
the clamp value during the black reference period at the begin-
ning of every line.
The minimum clamp capacitor value is determined by the maxi-
mum droop the LM9823 can tolerate while converting one sensor
line. The minimum clamp capacitor value is much smaller for CDS
mode applications than it is for CIS mode applications.
Figure 5. Input Circuitry
The LM9823 input current is considerably less when the LM9823
is operating in CDS mode. In CDS mode, the LM9823 average
input current is no more than 25nA. With CDS disabled, which will
likely be the case when CIS sensors are used, the LM9823 input
impedance will be 1/(f
Sample
*C
S
). where f
Sample
is the sample
rate of the analog input and C
S
is 2pF.
6.1.1 CDS mode Minimum Clamp Capacitor Calculation:
The following equation takes the maximum leakage current into
V
DAC
Equation 2. Offset DAC Output Voltage
9.75mV
(value in B4 - B0)
=
Offset
Equation 3. Offset in ADC Output Codes
20LSBs
(value in B4 - B0)
PGA Gain
=
V
DAC
DAC
Offset
G
PGA
Σ
+
+
ADC
+
+
+
+
V
OS3
V
OS2
Σ
Σ
G
B
+
+
V
OS1
V
IN
Σ
x3 Boost
1V/V or
3V/V
PGA
0.93V/V to
3V/V
D
OUT
D
OUT
V
IN
V
OS1
+
(
)
G
B
V
DAC
V
OS2
+
+
(
)
G
PGA
V
OS3
+
(
)
C
=
D
OUT
V
IN
G
B
V
DAC
+
(
)
G
PGA
C
=
V
IN
+
CDS Mode Input Circuitry
Inside LM9823
Inside LM9823
C
CLAMP
OS C
S
C
I
P1
P2
V
IN
+
CIS Mode Input Circuitry
C
CLAMP
OS
C
S
C
I
P1
P2
V
REF
Applications Information
(Continued)
L
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LM9830 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9830 36-Bit Color Document Scanner
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