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參數(shù)資料
| 型號： | LMU217JC25 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | GIGATRUE 550 CAT PATCH CBL NO BOOT 30FT YW 25 PK |
| 中文描述： | 16-BIT, DSP-MULTIPLIER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 178K |
| 代理商： | LMU217JC25 |
DEVICES INCORPORATED
LMU217
16 x 16-bit Parallel Multiplier
16 x 16-bit Parallel multiplier
Multipliers
08/16/2000–LDS.217-H
1
RND is loaded on the rising edge of
CLK, provided either ENA or ENB are
LOW. RND, when HIGH, adds ‘1’ to
the most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.
At the output, the Right Shift control
(RS) selects either of two output formats.
RS LOW produces a 31-bit product
with a copy of the sign bit inserted in the
MSB postion of the least significant half.
RS HIGH gives a full 32-bit product. Two
16-bit output registers are provided to
hold the most and least significant
halves of the result (MSP and LSP) as
defined by RS. These registers are
loaded on the rising edge of CLK, subject
to the ENR control. When ENR is
HIGH, clocking of the result registers is
prevented.
For asynchronous output, these registers
may be made transparent by setting the
feed through control (FT) HIGH and
ENR LOW.
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP outputs
to be driven by the most significant half
of the result. MSPSEL HIGH routes the
least significant half of the result to the
MSP pins. In addition, the LSP is
available via the B port through a sepa-
rate three-state buffer.
K
25 ns Worst-Case Multiply Time
K
Low Power CMOS Technology
K
Replaces Cypress CY7C517,
IDT 7217L, and AMD Am29517
K
Single Clock Architecture with
Register Enables
K
Two’s Complement, Unsigned, or
Mixed Operands
K
Three-State Outputs
K
68-pin PLCC, J-Lead
FEATURES
DESCRIPTION
DEVICES INCORPORATED
The
LMU217
is a high-speed, low
power 16-bit parallel multiplier.
The LMU217 produces the 32-bit prod-
uct of two 16-bit numbers. Data present
at the A inputs, along with the TCA
control bit, is loaded into the A register
on the rising edge of CLK. B data and
the TCB control bit are similarly
loaded. Loading of the A and B
registers is controlled by the ENA and
ENB controls. When HIGH, these con-
trols prevent application of the clock to
the respective register. The TCA and
TCB controls specify the operands as
two’s complement when HIGH, or
unsigned magnitude when LOW.
LMU217 B
LOCK
D
IAGRAM
A REGISTER
B REGISTER
REGISTER
RESULT
R
ENA
ENB
RND
FT
16
16
32
16
16
16
OEM
OEL
A
15-0
R
31-16
TCA
TCB
RS
ENR
FORMAT ADJUST
16
B
15-0
/
R
15-0
MSPSEL
CLK
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PDF描述 |
|---|---|
| LMU217JC35 | GIGATRUE 550 CAT6 PATCH 50 FT, NON BOOT, YELLOW |
| LMU217 | 16 x 16-bit Parallel multiplier |
| LMU8UJC35 | 8 x 8-bit Parallel Multiplier |
| LMU8UJC50 | 8 x 8-bit Parallel Multiplier |
| LMU8UPC35 | 8 x 8-bit Parallel Multiplier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMU217JC35 | 制造商:LOGIC 制造商全稱:LOGIC 功能描述:16 x 16-bit Parallel multiplier |
| LMU217JC45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| LMU217JC55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| LMU217JC65 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| LMU217KC45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
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