Application Notes
(Continued)
CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS
IN COMPARATOR APPLICATIONS
Feedback to almost any pin of a comparator can result in
oscillation. In addition, when the input signal is a slow volt-
age ramp or sine wave, the comparator may also burst into
oscillation near the crossing point. To avoid oscillation or
instability, PCB layout should be engineered thoughtfully.
Several precautions are recommended:
1. Power supply bypassing is critical, and will improve sta-
bility and transient response. Resistance and inductance
from power supply wires and board traces increase
power supply line impedance. When supply current
changes, the power supply line will move due to its im-
pedance. Large enough supply line shift will cause the
comparator to mis-operate. To avoid problems, a small
bypass capacitor, such as 0.1uF ceramic, should be
placed immediately adjacent to the supply pins. An addi-
tional 6.8μF or greater tantalum capacitor should be
placed at the point where the power supply for the com-
parator is introduced onto the board. These capacitors
act as an energy reservoir and keep the supply imped-
ance low. In dual supply application, a 0.1μF capacitor is
recommended to be placed across V
+
and V
pins.
2. Keep all leads short to reduce stray capacitance and lead
inductance. It will also minimize any unwanted coupling
from any high-level signals (such as the output). The
comparators can easily oscillate if the output lead is
inadvertently allowed to capacitively couple to the inputs
via stray capacitance. This shows up only during the
output voltage transition intervals as the comparator
changes states. Try to avoid a long loop which could act
as an inductor (coil).
3. It is a good practice to use an unbroken ground plane on
a printed circuit board to provide all components with a
low inductive ground connection. Make sure ground
paths are low-impedance where heavier currents are
flowing to avoid ground level shift. Preferably there
should be a ground plane under the component.
4. The output trace should be routed away from inputs. The
ground plane should extend between the output and
inputs to act as a guard.
5. When the signal source is applied through a resistive
network to one input of the comparator, it is usually
advantageous to connect the other input with a resistor
with the same value, for both DC and AC consideration.
Input traces should be laid out symmetrically if possible.
6. All pins of any unused comparators should be tied to the
negative supply.
Typical Applications
POSITIVE PEAK DETECTOR
A positive peak detect circuit is basically a comparator oper-
ated in a unity gain follower configuration, with a capacitor as
a load to maintain the highest voltage. A diode is added at
the output to prevent the capacitor from discharging through
the output, and a 1M
resistor added in parallel to the
capacitor to provide a high impedance discharge path. When
the input V
increases, the inverting input of the comparator
follows it, thus charging the capacitor. When it decreases,
the cap discharges through the 1M
resistor. The decay
time can be modified by changing the resistor. The output
should be accessed through a follower circuit to prevent
loading.
NEGATIVE PEAK DETECTOR
For the negative detector, the output transistor of the com-
parator acts as a low impedance current sink. Since there is
no pull-up resistor, the only discharge path will be the 1M
resistor and any load impedance used. Decay time is
changed by varying the 1M
resistor.
20080044
20080043
FIGURE 4. Non-Inverting Comparator with Hysteresis
20080054
FIGURE 5. Positive Peak Detector
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