參數(shù)資料
型號(hào)： LMX2470
廠商： National Semiconductor Corporation
英文描述： 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL
中文描述： 2.6 GHz的Δ-Σ分?jǐn)?shù)N與800兆赫整數(shù)N分頻PLL鎖相環(huán)
文件頁(yè)數(shù)： 22/36頁(yè)
文件大?。?/td> 453K
代理商： LMX2470
Functional Description
(Continued)
1.6.4 RF PLL Fastlock Reference Table and Example
The table below shows most of the trade-offs involved in
choosing a steady-state charge pump current (RF_CPG),
the Fastlock charge pump current (RF_CPF), and the Cycle
Slip Reduction Factor (CSR).
Parameter
RF_CPG
Advantages to Choosing Smaller
1. Allows capacitors in loop filter to be smaller
values making it easier to find physically smaller
components and components with better dielectric
properties.
2. Allows a larger loop bandwidth multiplier for
fastlock, or a higher cycle slip reduction factor.
The only reason not to always choose this to 1600
μA is to make it such that no resistor is required for
fastlock. For 3rd and 4th order filters, it is not
possible to keep the filter perfectly optimized by
simply switching in a resistor for fastlock.
Do not choose this any larger than necessary to
eliminate cycle slipping. Keeping this small allows a
larger loop bandwidth multiplier for fastlock.
Advantages to Choosing Larger
Phase noise, especially within the loop bandwidth of
the system
will be slightly worse for lower charge pump
currents.
RF_CPF
This allows the maximum possible benefit for
fastlock.
CSR
This will eliminate cycle slips better.
The above table shows various combinations for using
RF_CPG, RF_CPF, and CSR. Although this table does not
show all possible combinations, it does show all the modes
that give the best possible performance. To use this table,
choose a CSR factor on the horizontal axis, then a fastlock
loop bandwidth multiplier on the vertical axis, and the table
will show all possible combinations of steady state current,
Fastlock current, and what resistor value (R2’) to use during
Fastlock. In order to better illustrate the cycle slipping and
Fastlock circuitry, consider the following example:
Crystal Reference
Comparison Frequency
10 MHz x 2 = 20 MHz (OSC2X = 1)
Output Frequency
PLL Loop Bandwidth
Loop Filter Order
10 MHz
1930 – 1990 MHz
10 KHz
4th ( i.e. 7 components )
The comparison frequency is 20 MHz and the loop band-
width is 10 KHz. 20 MHz is a good comparison freqeuncy to
use because it yields the best phase noise performance.
This ratio of the comparison frequency to the loop bandwidth
is 2000, so cycle slipping will occur and degrade the lock
time, unless something is done to prevent it. Because the
filter is fourth order, it would be difficult to keep the loop filter
optimized if the loop gain multiplier, K was not one. For this
reason, choosing a loop gain multiplier of one makes sense.
One solution is to set the steady state current to be 100 μA,
and the fastlock current to be 1600 μA. The CSR factor could
be set to 1/16 and reduce this ratio to 2000/16 = 125.
However, using 100 μA charge pump current has phase
noise that is significantly worse than the higher charge pump
current modes. A better solution would be to use 200 μA
current and 1600 μA X2 ( using PDCP = X2 Fastlock ), since
the 200 μAmode will have better phase noise. Depending on
how important phase noise is, it could make sense to use a
higher steady state current. Using 800 μA steady state cur-
rent provides much better phase noise than 200 uA( about 5
dB ), but then the cycle slip reduction factor would need to be
reduced to 4. In general, it is good practice to use the PDCP
= X2 fastlock mode whenever cycle slip reduction is used, so
that the best phase noise can be achieved. If the
1
4
CSR
factor is used, then the ratio of comparison frequency to loop
bandwidth in fastlock is reduced to 250. There may be some
cycle slipping, but the phase noise benefit of using the higher
charge pump current may be worth it. If phase noise is even
more important, it might even make sense to have a steady
state current of 1600 μA and use a CSR factor of
1
2
and the
PDCP mode of X2 Fastlock. Another consideration is that
the comparison frequency could be lowered in the steady
state mode to reduce cycle slipping. This sacrifices phase
noise for lock time. In general, using Fastlock and CSR is not
the same for every application. There is a trade-off of lock
time vs. phase noise. It might be tempting to try to achieve
the best Fastlock benefit by using a K value of 32. Even if the
loop filter could be kept well optimized in Fastlock, this
hypothetical design would probably switch very fast when
the Fastlock was engaged, but then when Fastlock is disen-
gaged, a large frequency glitch would appear, and the ma-
jority of the lock time would consist of waiting for this glitch to
settle out. Although this would definitely improve the lock
time, even accounting for the glitch, the same result could
probably be obtained by using a lower K value, like 8, and
having better phase noise instead.
L
www.national.com
22
相關(guān)PDF資料
PDF描述
LMX2470SLEX 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL
LMX2485 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485E 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485ESQ 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485ESQX 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2470EVAL 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 LMX2470 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
LMX2470SLEX 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
LMX2470SLEX/NOPB 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
LMX2471 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL
LMX2471 WAF 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*