參數(shù)資料
型號: LMX3162VBHX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通信及網絡
英文描述: Single Chip Radio Transceiver
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP48
封裝: 7 X 7 MM, PLASTIC, QFP-48
文件頁數(shù): 13/18頁
文件大小: 399K
代理商: LMX3162VBHX
Swallow Counter Divide Ratio (A-Counter)
(Continued)
Note:
Divide ratio must be from 0 to 63, and B must be
A.
Programmable Counter Divide Ratio (B-Counter)
Divide Ratio, B
3
4
*
127
N13
0
0
*
1
N12
0
0
*
1
N11
0
0
*
1
N10
0
0
*
1
N9
0
1
*
1
N8
1
0
*
1
N7
1
0
*
1
Note:
Divide ratio must be from 3 to 127, and B must be
A.
Programmable Reference Divider (R-Counter)
If the control bits are “10”, data is transferred from the 20-bit shift register into a latch, which sets the 5-bit R-counter. The serial
data format is shown below.
MSB
19
REGISTER’S BIT MAPPING
12
11
10
LSB
18
17
16
15
14
13
9
8
7
6
5
4
3
2
1
0
RESERVED
R-COUNTER’s Divide
Ratio
R5
R4
R3
C2
C1
X
X
X
X
X
X
X
X
X
X
X
X
X
R2
R1
1
0
Note:
X = Don’t Care Condition
Reference Counter Divide Ratio (R-Counter)
Divide Ratio, R
3
4
*
31
R5
0
0
*
1
R4
0
0
*
1
R3
0
1
*
1
R2
1
0
*
1
R1
1
0
*
1
Note:
Divide ratio must be from 3 to 31.
Pulse Swallow Function
f
vco
:
B:
A:
f
OSC
: Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of binary 5-bit programmable reference counter (3 to 31)
P:
Preset modulus of dual modulus prescaler (32 or 64)
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 7-bit programmable counter (3 to 127)
Preset divide ratio of binary 6-bit swallow counter (0
A
P, A
B)
Receiver Functional Description
The simplified block diagram below shows the mixer, IF amplifier, limiter, and discriminator. In addition, the DC compensation cir-
cuit, doubler, and voltage regulator for an external LNA stage are shown.
L
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13
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