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參數(shù)資料
| 型號： | LMX3162VBHX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Single Chip Radio Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, QFP-48 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 399K |
| 代理商： | LMX3162VBHX |
Loop Filter Design Consideration
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2 The open loop
gain is the product of the phase comparator gain (K
φ
), the
VCO gain (K
vco
/s), and the loop filter gain Z(s) divided by the
gain of the feedback counter modulus (N). The passive loop
filter configuration used is displayed in Figure 3 while the
complex impedance of the filter is given in Equation (2)
PASSIVE LOOP FILTER
Open loop gain = H(s) G(s) =
θ
i/
θ
e = K
φ
Z(s)K
VCO
/Ns
(1)
(2)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
(3)
and
T2 = R2
C2
(4)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency,
ω
, the filter time constants T1 and T2,
and the design constants K
φ
, K
vco
, and N.
(5)
From Equations (3), (4) we can see that the phase term will
be dependent on the single pole and zero such that the
phase margin is determined in Equation (6)
φ
(
ω
) = tan
1
(
ω
T 2) tan
1
(
ω
T 1) + 180
(6)
DS100929-8
FIGURE 1. Conventional PLL Architecture
DS100929-9
FIGURE 2. PLL Linear Model
DS100929-10
FIGURE 3. Passive Loop Filter
L
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