參數(shù)資料
型號: LP2995LQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: DDR Termination Regulator
中文描述: BUS TERMINATOR SUPPORT CIRCUIT, PQCC16
封裝: LLP-16
文件頁數(shù): 10/13頁
文件大?。?/td> 291K
代理商: LP2995LQ
PCB Layout Considerations
1.
AVIN and PVIN should be tied together for optimal per-
formance. A local bypass capacitor should be placed as
close as possible to the PVIN pin.
2.
GND should be connected to a ground plane with mul-
tiple vias for improved thermal performance.
3.
V
SENSE
should be connected to the V
TT
termination bus
at the point where regulation is required. For mother-
board applications an ideal location would be at the
center of the termination bus.
VDDQ can be connected remotely to the VDDQ rail
input at either the DIMM or the Chipset. This provides
the most accurate point for creating the reference volt-
age.
V
should be bypassed with a 0.01 μF or 0.1 μF
ceramic capacitor for improved performance. This ca-
pacitor should be located as close as possible to the
V
REF
pin.
4.
5.
L
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