參數(shù)資料
型號: LP2995LQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: DDR Termination Regulator
中文描述: BUS TERMINATOR SUPPORT CIRCUIT, PQCC16
封裝: LLP-16
文件頁數(shù): 6/13頁
文件大?。?/td> 291K
代理商: LP2995LQ
Block Diagram
20039301
Description
The LP2995 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-3. The
LP2995 is capable of sinking and sourcing current at the
output V
TT
, regulating the voltage to equal VDDQ / 2. A
buffered reference voltage that also tracks VDDQ / 2 is
generated on the V
pin for providing a global reference to
the DDR-SDRAM and Northbridge Chipset. V
is designed
to track the V
voltage with a tight tolerance over the
entire current range while preventing shoot through on the
output stage.
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR RAM. The most common
form of termination is Class II single parallel termination. This
involves using one Rs series resistor from the chipset to the
memory and one Rt termination resistor. This implementa-
tion can be seen below in
Figure 1
.
Typical values for R
S
and R
T
are 25 Ohms although these
can be changed to scale the current requirements from the
LP2995. For determination of the current requirements of
DDR-SDRAM termination please refer to the accompanying
application notes.
20039308
FIGURE 1.
L
www.national.com
6
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