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參數(shù)資料
| 型號： | LP3470 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Tiny Power On Reset Circuit |
| 中文描述： | 微小型電源電路復(fù)位 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 157K |
| 代理商： | LP3470 |
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC
Voltage
Reset Voltage
Output Current (Reset)
0.3V to +6V
0.3V to +6V
10 mA
Operating Temperature Range
LP3470
LP3470I
Junction Temperature (T
Jmax
)
Power Dissipation (T
A
= 25C) (Note
2)
θ
JA
(Note 2)
Storage Temp. Range
Lead Temp. (Soldering, 5 sec)
ESD Rating (Note 3)
20C to +85C
40C to +85C
125C
300 mW
280C/W
65C to +150C
260C
2 kV
Electrical Characteristics
Limits in standard typeface are for T
= 25C, and limits in
boldface
type apply over the full operating temperature range, unless
otherwise specified. V
CC
= +2.4V to +5.0V unless otherwise noted.
Symbol
Parameter
Conditions
V
CC
Operating Voltage Range
I
CC
V
CC
Supply Current
V
CC
= 4.5V
V
RTH
Reset Threshold Voltage
(Note 6)
LP3470I
Typ
(Note 4)
Min
(Note 5)
0.5
Max
(Note 5)
5.5
30
1.01 V
RTH
1.01 V
RTH
1.01 V
RTH
1.015 V
RTH
65
300
3.5
Units
V
μA
16
LP3470
V
RTH
0.99 V
RTH
0.99 V
RTH
0.99 V
RTH
0.985 V
RTH
15
V
V
RTH
V
HYST
t
PD
t
RP
Hysteresis Voltage (Note 7)
V
CC
to Reset Delay
Reset Timeout Period (Note
8)
Reset Output Voltage Low
35
100
2
mV
μs
V
CC
falling at 1 mV/μs
C
1
= 1 nF
1.0
ms
V
OL
V
CC
= 0.5V; I
OL
= 30 μA
V
CC
= 1.0V; I
OL
= 100 μA
V
CC
=V
RTH
100 mV; I
OL
= 4
mA
0.1
0.1
0.4
V
R
1
I
LEAK
External Pull-up Resistor
Reset Output Leakage
Current
20
0.15
0.68
68
1
6
k
μA
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device
beyond its operating conditions.
Note 2:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(Maximum Junction Temperature),
θ
JA
(Junction to Am-
bient Thermal Resistance), and T
A
(Ambient Temperature). The maximum allowable power dissipation at any temperature is P
Dmax
= (T
Jmax
T
A
)/
θ
JA
or the number
given in the Absolute Maximum Ratings, whichever is lower.
Note 3:
The Human Body Model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin.
Note 4:
Typical numbers are at 25C and represent the most likely parametric norm.
Note 5:
Min. and Max. limits in standard typeface are 100% production tested at 25C. Min. and Max. limits in boldface are guaranteed through correlation using Sta-
tistical Quality Control (SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 6:
Factory-trimmed reset thresholds are available in 50 mV increments from 2.4V to 5.0V. Contact your National Semiconductor representative.
Note 7:
V
HYST
affects the relation between V
CC
and Reset as shown in the timing diagram.
Note 8:
t
RP
is programmable by varying the value of the external capacitor (C
1
) connected to pin SRT. The equation is: t
RP
= 2000 x C
1
(C
1
in μF and t
RP
in ms).
www.national.com
3
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