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參數(shù)資料
| 型號： | LP3470 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Tiny Power On Reset Circuit |
| 中文描述： | 微小型電源電路復位 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 157K |
| 代理商： | LP3470 |
Functional Block Diagram
Application Information
Reset Timeout Period
The Reset Timeout Period (t
) is programmable using an
external capacitor (C
) connected to pin SRT of LP3470. A
Ceramic chip capacitor rated at or above 10V is sufficient.
The Reset Timeout Period (t
RP
) can be calculated using the
following formula:
t
RP
(ms) = 2000 x C
1
(μF).
For example a C
1
of 100 nF will achieve a t
of 200 ms. If
no delay due to t
is needed in a certain application, the pin
SRT should be left floating.
Reset Output
In applications like microprocessor (μP) systems, errors
might
occur
in
system
operation
power-down, or brownout conditions. It is imperative to
monitor the power supply voltage in order to prevent these
errors from occurring.
The LP3470 asserts a reset signal whenever the V
supply
voltage is below a threshold (V
RTH
) voltage. Reset is guaran-
teed to be a logic low for V
>
exceeds the
reset threshold, the reset is kept asserted for a time period
(t
) programmed by an external capacitor (C
); after this in-
terval Reset goes to logic high. If a brownout condition oc-
curs (monitored voltage falls below the reset threshold minus
a small hysteresis), Reset goes low. When V
returns
above the reset threshold, Reset remains low for a time pe-
riod t
RP
before going to logic high.
during
power-up,
Pull-up Resistor Selection
The LP3470’s Reset output structure is a simple open-drain
N-channel MOSFET switch. A pull-up resistor (R
1
) should be
connected to V
CC
.
R
should be large enough to limit the current through the
output MOSFET (Q
) below 10 mA. A resistor value of more
than 680
guarantees this. R
should also be small enough
to ensure a logic high while supplying all the leakage current
through the Reset pin.Aresistor value of less than 68k
sat-
isfies this condition. A typical pull-up resistor value of 20 k
is sufficient in most applications.
Negative-Going V
CC
Transients
The
LP3470
is
negative-going V
transients (glitches). The Typical Oper-
ating Characteristics show the Maximum Transient Duration
vs. Negative Transient Amplitude (graph titled Transient Re-
jection), for which reset pulses are not generated. This graph
shows the maximum pulse width a negative-going V
tran-
sient may typically have without causing a reset pulse to be
issued. As the transient amplitude increases (i.e. goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. A 0.1 μF bypass capacitor mounted
close to V
CC
provides additional transient immunity.
relatively
immune
to
short
duration
DS100016-3
www.national.com
5
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