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參數(shù)資料
| 型號(hào)： | LP61L1024S-12 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
| 中文描述： | 128K的× 8位3.3V的高速低虛擬通道連接CMOS SRAM的 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 178K |
| 代理商： | LP61L1024S-12 |
LP61L1024
(August, 2002, Version 2.1)
5
AMIC Technology, Inc.
AC Characteristics (continued)
Symbol
Parameter
LP61L1024-12
LP61L1024-15
Unit
Min.
Max.
Min.
Max.
Write Cycle
t
WC
Write Cycle Time
12
-
15
-
ns
t
CW
Chip Enable to End of Write
10
-
12
-
ns
t
AS
Address Setup Time of Write
0
-
0
-
ns
t
AW
Address Valid to End of Write
10
-
12
-
t
WP
Write Pulse Width
8
-
10
-
ns
t
WR
Write Recovery Time
0
-
0
-
ns
t
WHZ
Write to Output in High Z
0
7
0
8
ns
t
DW
Data to Write Time Overlap
8
-
10
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
ns
t
OW
Output Active from End of Write
5
-
5
-
ns
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
, and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
Timing Waveforms
Read Cycle 1
(1, 2, 4)
t
RC
t
OH
t
AA
t
OH
Address
D
OUT
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PDF描述 |
|---|---|
| LP61L1024S-15 | 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
| LP61L1024U-15 | 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
| LP61L1024U-12 | 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
| LP61L256BS-12 | 32K X 8 Bit High SPEED LOW VCC CMOS SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP61L1024S-15 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
| LP61L1024U-12 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
| LP61L1024U-15 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
| LP61L1024V-12 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
| LP61L1024V-15 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
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