參數(shù)資料
型號(hào): LP61L256BV-12
廠商: AMIC Technology Corporation
英文描述: 32K X 8 Bit High SPEED LOW VCC CMOS SRAM
中文描述: 32K的× 8位高速CMOS SRAM的低虛擬通道連接
文件頁(yè)數(shù): 1/11頁(yè)
文件大?。?/td> 132K
代理商: LP61L256BV-12
LP61L256B Series
32K X 8 Bit High SPEED LOW VCC CMOS SRAM
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.
Features
n
Single +3.3 volt power supply
n
Access times: 12 ns (max.)
n
Current: Operating: 100mA (max.)
Standby:
n
Full static operation, no clock or refreshing required
10mA (max.)
n
All inputs and outputs directly TTL compatible
n
Common I/O using three-state output
n
Data retention voltage: 2V (min.)
n
Available in 28-pin SOJ and TSOP packages
General Description
The LP61L256B is a high-speed, low-power 262,144-bit
static random access memory organized as 32,768 words
by 8 bits that operates on a single 3.3V power supply.
Input and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when CE
is at a high level, independent of the other input levels.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Pin Configurations
n
SOJ
n
TSOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
GND
I/O
4
I/O
5
I/O
6
I/O
8
A11
A9
A8
A13
VCC
A10
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
7
OE
WE
L
1
14
15
28
CE
Pin No.
Pin
Name
Pin No.
Pin
Name
1
OE
2
A11
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
20
17
19
18
21
16
15
A9
A8
A13
WE
VCC
A14
A12
A10
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
CE
GND
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