參數(shù)資料
型號(hào): LP61L1024S-15
廠商: AMIC Technology Corporation
英文描述: 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
中文描述: 128K的× 8位3.3V的高速低虛擬通道連接CMOS SRAM的
文件頁(yè)數(shù): 8/16頁(yè)
文件大小: 178K
代理商: LP61L1024S-15
LP61L1024
(August, 2002, Version 2.1)
7
AMIC Technology, Inc.
Timing Waveforms (continued)
Read Cycle 4
(1)
t
RC
Address
OE
t
AA
t
OE
t
OLZ5
t
ACE1
t
CLZ25
t
ACE2
t
CLZ25
t
CHZ25
t
OHZ5
t
CHZ15
t
OH
CE1
CE2
D
OUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = V
IL
and CE2 = V
IH
.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
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