參數(shù)資料
型號(hào)： LP62E16512U-70LLT
廠商： AMIC Technology Corporation
英文描述： Shielded Paired Cable; Number of Conductors:2; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:1; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： 為512k × 16位低電壓CMOS的SRAM
文件頁數(shù)： 11/14頁
文件大?。?/td> 147K
代理商： LP62E16512U-70LLT
LP62E16512-I Series
PRELIMINARY
(April, 2002, Version 0.0)
10
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
t
WC
t
AW
Address
CS
1
t
WR
3
t
CW1 ,
t
CW2
t
BW
2
t
AS
1
DATA IN
DATA OUT
WE
HB, LB
t
WP
t
DW
t
DH
t
OW
t
WHZ
4
CS
2
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
, t
BW
) of a low
3. t
WR
is measured from the earliest of
the Write cycle.
4. OE level is high or low.
5. Transition is measured
±
200mV from steady state. This parameter is sampled and not 100% tested.
1
CS , WE and (HB and , or LB ) or a high CS
2
.
CS or WE or (HB and , or LB ) going high or CS
2
going Low to the end of
1
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