參數(shù)資料
型號(hào): LP62E16512U-70LLT
廠商: AMIC Technology Corporation
英文描述: Shielded Paired Cable; Number of Conductors:2; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:1; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述: 為512k × 16位低電壓CMOS的SRAM
文件頁數(shù): 14/14頁
文件大?。?/td> 147K
代理商: LP62E16512U-70LLT
LP62E16512-I Series
PRELIMINARY
(April, 2002, Version 0.0)
13
AMIC Technology, Inc.
Package Information
48LD CSP ( 8 x 10 mm ) Outline Dimensions
(48TFBGA)
unit: mm
A
1
A
B
C
D
E
F
G
H
TOP VIEW
Ball#A1 CORNER
SIDE VIEW
C
SEATING PLANE
A
A
B
C
D
E
F
G
H
1
2
3
4
5
6
1
2
3
4
5
6
C
0.10
0.25
S
C
S
A B
b (48X)
BOTTOM VIEW
Ball*A1 CORNER
E
E
1
e
B
e
D
1
D
A
0.20(4X)
0
Dimensions in mm
MIN.
NOM.
---
---
0.20
0.25
0.48
0.53
7.90
8.00
9.90
10.00
---
3.75
---
5.25
---
0.75
0.30
0.35
Symbol
MAX.
A
A
1
A
2
D
E
D
1
E
1
e
b
1.20
0.30
0.58
8.10
10.10
---
---
---
0.40
Notes:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
5. BALL PAD OPENING OF SUBSTRATE IS
Φ
0.3mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS
Φ
0.3mm (NSMD)
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