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參數(shù)資料
| 型號： | LP62S1024BU-70LLT |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | SWITCH KEYLOCK DPDT 4A 90DEG |
| 中文描述： | 128K的× 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 189K |
| 代理商： | LP62S1024BU-70LLT |
LP62S1024A-T Series
(August, 2001, Version 1.0)
10
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
CE1
CE2
D
IN
t
DH
t
DW
(4)
(4)
t
CW5
t
AW
t
WR3
WE
D
OUT
t
WHZ7
t
WP2
t
CW5
t
AS1
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
) of a low CE1, a high CE2 and a low WE .
3. t
WR
is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. t
CW
is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. (OE = V
IL
)
7. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
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