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參數(shù)資料
| 型號： | LP62S1024BU-70LLT |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | SWITCH KEYLOCK DPDT 4A 90DEG |
| 中文描述： | 128K的× 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 189K |
| 代理商： | LP62S1024BU-70LLT |
LP62S1024A-T Series
(August, 2001, Version 1.0)
17
AMIC Technology, Inc.
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
A
1
A
2
A
B
C
D
E
F
G
H
TOP VIEW
Ball#A1 CORNER
SIDE VIEW
C
SEATING PLANE
/
A
(
A
B
C
D
E
F
G
H
1
2
3
4
5
6
1
2
3
4
5
6
C
0.10
0.25
S
C
S
A B
b (36X)
BOTTOM VIEW
Ball*A1 CORNER
E
E
1
e
B
e
D
1
D
A
0.20(4X)
0
Dimensions in mm
MIN.
NOM.
1.00
1.10
0.16
0.21
0.48
0.53
5.80
6.00
7.80
8.00
---
3.75
---
5.25
---
0.75
0.25
0.30
Symbol
MAX.
A
A
1
A
2
D
E
D
1
E
1
e
b
1.20
0.26
0.58
6.20
8.20
---
---
---
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LP62S1024A-I | 128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024A-T | 128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024AV-55LLI | 128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024AV-55LLT | 128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024AV-70LLI | 128K X 8 BIT LOW VOLTAGE CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP62S1024BV-55LLI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024BV-55LLIF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024BV-55LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024BV-70LLI | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024BV-70LLIF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
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