參數(shù)資料
型號： LPC11U24FBD64/401
廠商： NXP Semiconductors
文件頁數(shù)： 41/74頁
文件大?。?/td> 0K
描述： IC MCU USB 64LQFP
產(chǎn)品培訓(xùn)模塊： Code Density for LPC11xx
標(biāo)準(zhǔn)包裝： 160
系列： LPC11Uxx
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 50MHz
連通性： I²C，Microwire，SPI，SSI，SSP，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 10K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤
其它名稱： 568-8461
LPC11U24FBD64/401,551
LPC11U2X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
46 of 74
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
[2]
The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.
[3]
See the LPC11Uxx user manual.
10.4 I/O pins
[1]
Applies to standard port pins and RESET pin.
10.5 I2C-bus
[1]
See the I2C-bus specification UM10204 for details.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4]
Cb = total capacitance of one bus line in pF.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[6]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
Table 14.
Dynamic characteristics: I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V VDD 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
pin configured as output
3.0
-
5.0
ns
tf
fall time
pin configured as output
2.5
-
5.0
ns
Table 15.
Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock
frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
tf
fall time
of both SDA and SCL
signals
Standard-mode
-300
ns
Fast-mode
20 + 0.1
C
b
300
ns
Fast-mode Plus
-
120
ns
tLOW
LOW period of the
SCL clock
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
Fast-mode Plus
0.5
-
s
tHIGH
HIGH period of the
SCL clock
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
Fast-mode Plus
0.26
-
s
tHD;DAT
data hold time
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
tSU;DAT
data set-up time
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
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