參數(shù)資料
型號: LPC1224FBD48/101,1
廠商: NXP Semiconductors
文件頁數(shù): 31/61頁
文件大?。?/td> 0K
描述: MCU 32BIT 32K FLASH 4K 48-LQFP
產(chǎn)品培訓(xùn)模塊: LPC1200 Series for Industrial Control
標(biāo)準(zhǔn)包裝: 250
系列: LPC1200
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 45MHz
連通性: I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,WDT
輸入/輸出數(shù): 39
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-LQFP
包裝: 托盤
其它名稱: 568-5153
LPC1224FBD48/201
LPC1224FBD48/201,1
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
37 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD(3V3) = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(3) System oscillator enabled with external clock input; IRC and system PLL disabled.
Fig 10. Sleep mode: Typical supply current IDD versus supply voltage VDD(3V3) for
different system clock frequencies
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
Fig 11. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD(3V3)
VDD(3V3) (V)
3.0
3.6
3.4
3.2
002aag188
2
3
1
4
5
IDD
(mA)
0
33 MHz
(2)
24 MHz
(2)
12 MHz
(1)
1 MHz
(3)
4 MHz
(3)
002aag190
20
40
30
50
IDD
(μA)
10
temperature (°C)
-40
85
35
10
60
-15
VDD(3V3) = 3.6 V
3.3 V
3.0 V
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LPC1224FBD64/101,151 制造商:NXP Semiconductors 功能描述:Bulk