參數(shù)資料
型號(hào): LPC1226FBD48/301,1
廠商: NXP Semiconductors
文件頁(yè)數(shù): 11/61頁(yè)
文件大小: 0K
描述: MCU 32BIT 96K FLASH 8K 48-LQFP
產(chǎn)品培訓(xùn)模塊: LPC1200 Series for Industrial Control
特色產(chǎn)品: LPC122x Cortex-M0 Microcontrollers
標(biāo)準(zhǔn)包裝: 250
系列: LPC1200
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 45MHz
連通性: I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,WDT
輸入/輸出數(shù): 39
程序存儲(chǔ)器容量: 96KB(96K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-LQFP
包裝: 托盤
其它名稱: 568-5161
LPC1226FBD48/301
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
19 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory
transfers.
Supports multiple DMA cycle types and multiple DMA transfer widths.
Performs all DMA transfers using the single AHB-Lite burst type.
7.8 CRC engine
The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
7.8.1 Features
Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
CRC-CCITT: x16 + x12 + x5 + 1
CRC-16: x16 + x15 + x2 + 1
CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
Programmable seed number setting.
Supports CPU programmed I/O or DMA back-to-back transfer.
Accept any size of data width per write: 8, 16 or 32-bit.
8-bit write: 1-cycle operation
16-bit write: 2-cycle operation (8-bit
2-cycle)
32-bit write: 4-cycle operation (8-bit
4-cycle)
7.9 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
7.9.1 Features
Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
7.10 UARTs
The LPC122x contains two UARTs. UART0 supports full modem control and RS-485/9-bit
mode and allows both software address detection and automatic hardware address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
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