參數(shù)資料
型號(hào)： LPC1226FBD48/301,1
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 15/61頁(yè)
文件大?。?/td> 0K
描述： MCU 32BIT 96K FLASH 8K 48-LQFP
產(chǎn)品培訓(xùn)模塊： LPC1200 Series for Industrial Control
特色產(chǎn)品： LPC122x Cortex-M0 Microcontrollers
標(biāo)準(zhǔn)包裝： 250
系列： LPC1200
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 45MHz
連通性： I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，POR，WDT
輸入/輸出數(shù)： 39
程序存儲(chǔ)器容量： 96KB（96K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-LQFP
包裝： 托盤
其它名稱： 568-5161
LPC1226FBD48/301
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
22 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Comparator outputs connect to two timers, allowing for the recording of comparison
event time stamps.
7.15 General purpose external event counter/timers
The LPC122x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes up to four capture inputs to trap the
timer value when an input signal transitions, optionally generating an interrupt.
7.15.1 Features
A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
Counter or timer operation.
Up to four capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
Supports timed DMA requests.
7.16 Windowed WatchDog timer (WWDT)
The purpose of the watchdog is to reset the microcontroller within a windowed amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
7.16.1 Features
Internally resets chip if not periodically reloaded.
Debug mode.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Safe operation: can be locked by software to be always on.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
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