參數(shù)資料
型號(hào)： LPC12D27FBD100/301
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 6/46頁(yè)
文件大?。?/td> 0K
描述： MCU 32BIT ARM CORTEX-M0 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： LPC1200
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 45MHz
連通性： I²C，IrDA，SPI，SSP，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
其它名稱： 568-8372
LPC12D27
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 20 September 2011
14 of 46
NXP Semiconductors
LPC12D27
32-bit ARM Cortex-M0 microcontroller
[1]
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.
[2]
Digital I/O pin; default: pull-up enabled, no hysteresis.
[3]
I2C-bus pins; 5 V tolerant; open-drain; default: no pull-up/pull-down, no hysteresis.
[4]
Digital I/O pin with RESET function; default: pull-up enabled, no hysteresis.
[5]
Digital I/O pin with analog function; default: pull-up enabled, no hysteresis.
[6]
Digital I/O pin with analog function and WAKEUP function; default: pull-up enabled, no hysteresis.
[7]
High-drive digital I/O pin; default: pull-up enabled, no hysteresis.
[8]
7.
Functional description
7.1 LPC1227 microcontroller
See the LPC122x data sheet for a detailed functional description of the LPC1227
microcontroller.
7.2 LCD driver
See the PCF8576 data sheet for a detailed functional description of the PCF8576D LCD
driver.
7.2.1 General description
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCF8576D communicates via the two-line
bidirectional I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes). Please refer to PCF8576D data sheet for
electrical data.
BP1
44
-
VLCD[8] O
LCD backplane output.
BP2
43
-
VLCD[8] O
LCD backplane output.
BP3
45
-
VLCD[8] O
LCD backplane output.
LCD_SDA
35
-
I/O
I2C-bus serial data input/output.
LCD_SCL
36
-
I/O
I2C-bus serial clock input.
SYNC
37
-
I/O
Cascade synchronization input/output.
CLK
38
-
I/O
External clock input/output.
VDD
39
-
1.8 V to 5.5 V power supply: Power supply voltage for the
PCF8576D.
VSS(LCD)
40
-
LCD ground.
VLCD
41
-
LCD power supply: LCD voltage.
Table 3.
LPC12D27 LQFP100 pin description …continued
Symbol
Pin
Start
logic
input
Reset
state
[1]
Type
Description
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