參數(shù)資料
型號(hào)： LPC1315FBD48,551
廠商： NXP Semiconductors
文件頁數(shù)： 30/77頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 32KB FLASH 48LQFP
標(biāo)準(zhǔn)包裝： 250
系列： LPC13xx
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 72MHz
連通性： I²C，Microwire，SPI，SSI，SSP，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-LQFP
包裝： 托盤
其它名稱： 568-9591
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
36 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
7.18.6.3
Code security (Code Read Protection - CRP)
This feature of the LPC1315/16/17/45/46/47 allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the Serial Wire
Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed,
CRP is invoked by programming a specific pattern into a dedicated flash location. IAP
commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC1315/16/17/45/46/47 user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC1315/16/17/45/46/47 user manual.
7.18.6.4
APB interface
The APB peripherals are located on one APB bus.
7.18.6.5
AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M3 to the flash memory, the main
static RAM, and the ROM.
7.18.6.6
External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
7.19 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M3. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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