參數(shù)資料
型號: LPC1317FBD64,551
廠商: NXP Semiconductors
文件頁數(shù): 17/77頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 64KB FLASH 64LQFP
標準包裝: 160
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 51
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 10K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 568-9596
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
24 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
7.
Functional description
7.1 On-chip flash programming memory
The LPC1315/16/17/45/46/47 contain up to 64 kB on-chip flash program memory. The
flash can be programmed using In-System Programming (ISP) or In-Application
Programming (IAP) via the on-chip boot loader software. Flash updates via USB are
supported as well.
The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
Individual pages of 256 byte each can be erased using the IAP erase page command.
7.2 EEPROM
The LPC1315/16/17/45/46/47 contain 2 kB or 4 kB of on-chip byte-erasable and
byte-programmable EEPROM data memory. The EEPROM can be programmed using
In-Application Programming (IAP) via the on-chip boot loader software.
7.3 SRAM
The LPC1315/16/17/45/46/47 contain a total of 8 kB, 10 kB, or 12 kB on-chip static RAM
memory.
7.4 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
IAP support for EEPROM
USB API (HID, CDC, and MSC drivers) (LPC1345/46/47 only)
Power profiles for configuring power consumption and PLL settings
Flash updates via USB supported (LPC1345/46/47 only)
7.5 Memory map
The LPC1315/16/17/45/46/47 incorporates several distinct memory regions, shown in the
following figures. Figure 8 shows the overall map of the entire address space from the
user program viewpoint following reset. The interrupt vector area supports address
remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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