1. 參數(shù)資料
    型號: LPC1343FBD48,151
    廠商: NXP Semiconductors
    文件頁數(shù): 14/74頁
    文件大小: 0K
    描述: IC MCU 32BIT 32KB FLASH 48LQFP
    產(chǎn)品培訓(xùn)模塊: LPCXpresso
    特色產(chǎn)品: LPC1300 Series Cortex-M3 MCUs
    標準包裝: 250
    系列: LPC13xx
    核心處理器: ARM? Cortex?-M3
    芯體尺寸: 32-位
    速度: 72MHz
    連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART,USB
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
    輸入/輸出數(shù): 40
    程序存儲器容量: 32KB(32K x 8)
    程序存儲器類型: 閃存
    RAM 容量: 8K x 8
    電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 48-LQFP
    包裝: 托盤
    配用: 622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
    其它名稱: 568-4945
    935289652151
    LPC1311_13_42_43
    All information provided in this document is subject to legal disclaimers.
    NXP B.V. 2012. All rights reserved.
    Product data sheet
    Rev. 5 — 6 June 2012
    21 of 74
    NXP Semiconductors
    LPC1311/13/42/43
    32-bit ARM Cortex-M3 microcontroller
    7.10 UART
    The LPC1311/13/42/43 contains one UART.
    Support for RS-485/9-bit mode allows both software address detection and automatic
    address detection using 9-bit mode.
    The UART includes a fractional baud rate generator. Standard baud rates such as
    115200 Bd can be achieved with any crystal frequency above 2 MHz.
    7.10.1 Features
    Maximum UART data bit rate of 4.5 MBit/s.
    16-byte receive and transmit FIFOs.
    Register locations conform to 16C550 industry standard.
    Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
    Built-in fractional baud rate generator covering wide range of baud rates without a
    need for external crystals of particular values.
    Fractional divider for baud rate control, auto baud capabilities and FIFO control
    mechanism that enables software flow control implementation.
    Support for RS-485/9-bit mode.
    Support for modem control.
    7.11 SSP serial I/O controller
    The LPC1311/13/42/43 contain one SSP controller. An additional SSP controller is
    available on the LPC1313FBD48/01 package.
    The SSP controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can
    interact with multiple masters and slaves on the bus. Only a single master and a single
    slave can communicate on the bus during a given data transfer. The SSP supports full
    duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
    slave and from the slave to the master. In practice, often only one of these data flows
    carries meaningful data.
    7.11.1 Features
    Maximum SSP speed of 36 Mbit/s (master) or 6 Mbit/s (slave)
    Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
    Semiconductor Microwire buses
    Synchronous serial communication
    Master or slave operation
    8-frame FIFOs for both transmit and receive
    4-bit to 16-bit frame
    7.12 I2C-bus serial I/O controller
    The LPC1311/13/42/43 contain one I2C-bus controller.
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